diff --git a/HYGON-0004-i386-Fix-some-c86-4g-m7-reservations.patch b/HYGON-0004-i386-Fix-some-c86-4g-m7-reservations.patch new file mode 100644 index 0000000000000000000000000000000000000000..b7f9f596df52a6d0661b2ff29fb276975637ca92 --- /dev/null +++ b/HYGON-0004-i386-Fix-some-c86-4g-m7-reservations.patch @@ -0,0 +1,353 @@ +From 961059a1232d767e878194385a756e267422a57d Mon Sep 17 00:00:00 2001 +From: Xin Liu +Date: Wed, 17 Jun 2026 03:28:39 +0000 +Subject: [PATCH 1/3] i386: Fix some c86-4g-m7 reservations + +Fix several existing c86-4g-m7 scheduling reservation issues. + +The fixes correct decode unit selection, branch and call execution units, +missing store resources for store or load/store forms, and several FPU +pipeline resource descriptions. They also rename a few reservations so the +template names better match the instructions they cover, and simplify +duplicate memory attribute checks. + +gcc/ChangeLog: + + * config/i386/c86-4g-m7.md (c86_4g_m7_imov_xchg): Adjust + reservation units. + (c86_4g_m7_imov_xchg_load): Ditto. + (c86_4g_m7_call): Ditto. + (c86_4g_m7_branch): Ditto. + (c86_4g_m7_branch_load): Ditto. + (c86_4g_m7_fp_spc_direct): Add missing store unit. + (c86_4g_m7_sse_pinsr_reg): Adjust reservation units. + (c86_4g_m7_avx512_insertx_ymm): Ditto. + (c86_4g_m7_avx512_insertx_ymem): Ditto. + (c86_4g_m7_avx512_insertx_zxmm): Ditto. + (c86_4g_m7_avx512_insertx_zxmem): Ditto. + (c86_4g_m7_avx512_abs_load): Add missing store unit. + (c86_4g_m7_avx_sign): Use combined FPU reservation. + (c86_4g_m7_avx_sign_load): Ditto. + (c86_4g_m7_avx_aes): Ditto. + (c86_4g_m7_avx_aes_load): Ditto. + (c86_4g_m7_extr_load): Rename to ... + (c86_4g_m7_extr_store): ... this and restrict to store memory. + (c86_4g_m7_avx_imul): Use combined FPU reservation. + (c86_4g_m7_avx_imul_mem): Ditto. + (c86_4g_m7_avx512_vpmovx_y_load): Add missing store unit. + (c86_4g_m7_avx_vpmovx_xx_load): Ditto. + (c86_4g_m7_avx512_sseadd_maxmin_xy): Rename to ... + (c86_4g_m7_avx512_sseadd_maxmin): ... this and simplify + memory attribute check. + (c86_4g_m7_avx512_sseadd_maxmin_xy_load): Rename to ... + (c86_4g_m7_avx512_sseadd_maxmin_load): ... this and simplify + memory attribute check. + (c86_4g_m7_avx512_sseadd_xy): Rename to ... + (c86_4g_m7_avx512_sseadd): ... this. + (c86_4g_m7_avx512_sseadd_xy_load): Rename to ... + (c86_4g_m7_avx512_sseadd_load): ... this. + (c86_4g_m7_sse_sseiadd_sadbw): Use combined FPU reservation. + (c86_4g_m7_sse_sseiadd_sadbw_mem): Ditto. + (c86_4g_m7_avx512_ssecmp_vp_z): Adjust reservation units. + (c86_4g_m7_avx512_ssecmp_vp_z_load): Ditto. + (c86_4g_m7_avx512_ssecmp_test_load): Ditto. + (c86_4g_m7_avx512_mskmov_k_m): Adjust latency. + +Signed-off-by: Xin Liu +--- + gcc/config/i386/c86-4g-m7.md | 70 ++++++++++++++++++------------------ + 1 file changed, 34 insertions(+), 36 deletions(-) + +diff --git a/gcc/config/i386/c86-4g-m7.md b/gcc/config/i386/c86-4g-m7.md +index 0fd8422422b..8c784a145bf 100644 +--- a/gcc/config/i386/c86-4g-m7.md ++++ b/gcc/config/i386/c86-4g-m7.md +@@ -117,14 +117,14 @@ (define_insn_reservation "c86_4g_m7_imov_xchg" 1 + (and (eq_attr "type" "imov") + (and (eq_attr "c86_decode" "vector") + (eq_attr "memory" "none")))) +- "c86-4g-m7-direct") ++ "c86-4g-m7-vector") + + (define_insn_reservation "c86_4g_m7_imov_xchg_load" 5 + (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "type" "imov") + (and (eq_attr "c86_decode" "vector") + (eq_attr "memory" "!none")))) +- "c86-4g-m7-direct,c86-4g-m7-load") ++ "c86-4g-m7-vector,c86-4g-m7-load") + + (define_insn_reservation "c86_4g_m7_imovx_cwde" 2 + (and (eq_attr "cpu" "c86_4g_m7") +@@ -322,20 +322,20 @@ (define_insn_reservation "c86_4g_m7_alu1_direct_load" 5 + (define_insn_reservation "c86_4g_m7_call" 1 + (and (eq_attr "cpu" "c86_4g_m7") + (eq_attr "type" "call,callv")) +- "c86-4g-m7-double,c86-4g-m7-ieu0|c86-4g-m7-bru0,c86-4g-m7-store") ++ "c86-4g-m7-double,c86-4g-m7-store,c86-4g-m7-bru0") + + ;; IBR + (define_insn_reservation "c86_4g_m7_branch" 1 + (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "type" "ibr") + (eq_attr "memory" "none"))) +- "c86-4g-m7-direct,c86-4g-m7-ieu0|c86-4g-m7-bru0") ++ "c86-4g-m7-direct,c86-4g-m7-bru0") + + (define_insn_reservation "c86_4g_m7_branch_load" 5 + (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "type" "ibr") + (eq_attr "memory" "load"))) +- "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu0|c86-4g-m7-bru0") ++ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-bru0") + + ;; LEA + (define_insn_reservation "c86_4g_m7_lea" 1 +@@ -451,7 +451,7 @@ (define_insn_reservation "c86_4g_m7_fp_spc_direct" 5 + (and (eq_attr "c86_decode" "direct") + (and (eq_attr "c86_attr" "other") + (eq_attr "memory" "store"))))) +- "c86-4g-m7-direct,c86-4g-m7-fpu3") ++ "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu3") + + (define_insn_reservation "c86_4g_m7_fp_spc" 6 + (and (eq_attr "cpu" "c86_4g_m7") +@@ -632,7 +632,7 @@ (define_insn_reservation "c86_4g_m7_sse_pinsr_reg" 1 + (and (eq_attr "c86_attr" "insr") + (and (eq_attr "prefix" "orig") + (eq_attr "memory" "none"))))) +- "c86-4g-m7-double,c86-4g-m7-ieu2,c86-4g-m7-fpu") ++ "c86-4g-m7-direct,c86-4g-m7-fpu") + + (define_insn_reservation "c86_4g_m7_sse_pinsr_reg_load" 3 + (and (eq_attr "cpu" "c86_4g_m7") +@@ -755,7 +755,7 @@ (define_insn_reservation "c86_4g_m7_avx512_insertx_ymm" 3 + (and (eq_attr "mode" "V8SF,V4DF,OI") + (and (eq_attr "prefix" "evex") + (eq_attr "memory" "none")))))) +- "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2") ++ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_0_2") + + (define_insn_reservation "c86_4g_m7_avx512_insertx_ymem" 10 + (and (eq_attr "cpu" "c86_4g_m7") +@@ -764,7 +764,7 @@ (define_insn_reservation "c86_4g_m7_avx512_insertx_ymem" 10 + (and (eq_attr "mode" "V8SF,V4DF,OI") + (and (eq_attr "prefix" "evex") + (eq_attr "memory" "load,both")))))) +- "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2") ++ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_0_2") + + (define_insn_reservation "c86_4g_m7_avx512_insertx_zxmm" 5 + (and (eq_attr "cpu" "c86_4g_m7") +@@ -773,7 +773,7 @@ (define_insn_reservation "c86_4g_m7_avx512_insertx_zxmm" 5 + (and (eq_attr "mode" "V16SF,V8DF,XI") + (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==16") + (match_operand 2 "register_operand")))))) +- "c86-4g-m7-double,c86-4g-m7-fpu_0_2x4,c86-4g-m7-fpu_0_2x4") ++ "c86-4g-m7-double,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2") + + (define_insn_reservation "c86_4g_m7_avx512_insertx_zxmem" 12 + (and (eq_attr "cpu" "c86_4g_m7") +@@ -782,7 +782,7 @@ (define_insn_reservation "c86_4g_m7_avx512_insertx_zxmem" 12 + (and (eq_attr "mode" "V16SF,V8DF,XI") + (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==16") + (match_operand 2 "memory_operand")))))) +- "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4,c86-4g-m7-fpu_0_2x4") ++ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2") + + (define_insn_reservation "c86_4g_m7_avx512_insertx_zymm" 1 + (and (eq_attr "cpu" "c86_4g_m7") +@@ -945,7 +945,7 @@ (define_insn_reservation "c86_4g_m7_avx512_abs_load" 8 + (and (eq_attr "c86_attr" "abs") + (and (eq_attr "prefix" "evex") + (eq_attr "memory" "load,both"))))) +- "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu") ++ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-fpu") + + ;; SIGN + (define_insn_reservation "c86_4g_m7_avx_sign" 1 +@@ -953,14 +953,14 @@ (define_insn_reservation "c86_4g_m7_avx_sign" 1 + (and (eq_attr "type" "sselog1") + (and (eq_attr "c86_attr" "sign") + (eq_attr "memory" "none")))) +- "c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu3") ++ "c86-4g-m7-direct,c86-4g-m7-fpu_0_3") + + (define_insn_reservation "c86_4g_m7_avx_sign_load" 8 + (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "type" "sselog1") + (and (eq_attr "c86_attr" "sign") + (eq_attr "memory" "!none")))) +- "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu3") ++ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_3") + + ;; BLEND/ABS/AES + (define_insn_reservation "c86_4g_m7_avx_blend" 1 +@@ -1001,7 +1001,7 @@ (define_insn_reservation "c86_4g_m7_avx_aes" 3 + (and (eq_attr "c86_attr" "aes") + (and (eq_attr "prefix" "!evex") + (eq_attr "memory" "none"))))) +- "c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu1") ++ "c86-4g-m7-direct,c86-4g-m7-fpu_0_1") + + (define_insn_reservation "c86_4g_m7_avx_aes_load" 10 + (and (eq_attr "cpu" "c86_4g_m7") +@@ -1009,7 +1009,7 @@ (define_insn_reservation "c86_4g_m7_avx_aes_load" 10 + (and (eq_attr "c86_attr" "aes") + (and (eq_attr "prefix" "!evex") + (eq_attr "memory" "load"))))) +- "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu1") ++ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1") + + ;; EXTR + (define_insn_reservation "c86_4g_m7_extr" 5 +@@ -1019,11 +1019,11 @@ (define_insn_reservation "c86_4g_m7_extr" 5 + (eq_attr "memory" "none")))) + "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1") + +-(define_insn_reservation "c86_4g_m7_extr_load" 12 ++(define_insn_reservation "c86_4g_m7_extr_store" 12 + (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "type" "sselog1,sselog,mmxcvt") + (and (eq_attr "c86_attr" "extr") +- (eq_attr "memory" "!none")))) ++ (eq_attr "memory" "store")))) + "c86-4g-m7-double,c86-4g-m7-store,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1") + + ;; SSECOMI +@@ -1075,14 +1075,14 @@ (define_insn_reservation "c86_4g_m7_avx_imul" 3 + (and (eq_attr "type" "sseimul") + (and (eq_attr "prefix" "!evex") + (eq_attr "memory" "none")))) +- "c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu3") ++ "c86-4g-m7-direct,c86-4g-m7-fpu_0_3") + + (define_insn_reservation "c86_4g_m7_avx_imul_mem" 10 + (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "type" "sseimul") + (and (eq_attr "prefix" "!evex") + (eq_attr "memory" "load")))) +- "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu3") ++ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_3") + + ;; SSEMOV + (define_insn_reservation "c86_4g_m7_avx512_mov_vmov" 1 +@@ -1122,7 +1122,7 @@ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_y_load" 10 + (and (eq_attr "prefix" "evex") + (and (eq_attr "mode" "OI,V8SF,V4DF") + (eq_attr "memory" "load,both")))))) +- "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2") ++ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-fpu_0_2x2") + + (define_insn_reservation "c86_4g_m7_avx512_vpmovx_z" 5 + (and (eq_attr "cpu" "c86_4g_m7") +@@ -1172,7 +1172,7 @@ (define_insn_reservation "c86_4g_m7_avx_vpmovx_xx_load" 8 + (and (eq_attr "c86_attr" "vpmovx") + (and (eq_attr "prefix" "!evex") + (eq_attr "memory" "load,both"))))) +- "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1|c86-4g-m7-fpu2") ++ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-fpu1|c86-4g-m7-fpu2") + + ;; EXPAND + (define_insn_reservation "c86_4g_m7_avx512_expand" 3 +@@ -1288,22 +1288,20 @@ (define_insn_reservation "c86_4g_m7_avx512_sseishft_vshift_load" 8 + + + ;; SSEADD +-(define_insn_reservation "c86_4g_m7_avx512_sseadd_maxmin_xy" 1 ++(define_insn_reservation "c86_4g_m7_avx512_sseadd_maxmin" 1 + (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "type" "sseadd,sse") + (and (eq_attr "c86_attr" "maxmin") + (and (eq_attr "prefix" "evex") +- (and (eq_attr "memory" "none") +- (eq_attr "memory" "none")))))) ++ (eq_attr "memory" "none"))))) + "c86-4g-m7-direct,c86-4g-m7-fpu_0_2") + +-(define_insn_reservation "c86_4g_m7_avx512_sseadd_maxmin_xy_load" 8 ++(define_insn_reservation "c86_4g_m7_avx512_sseadd_maxmin_load" 8 + (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "type" "sseadd,sse") + (and (eq_attr "c86_attr" "maxmin") + (and (eq_attr "prefix" "evex") +- (ior (eq_attr "memory" "load") +- (eq_attr "memory" "load")))))) ++ (eq_attr "memory" "load"))))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2") + + (define_insn_reservation "c86_4g_m7_avx_sseadd_maxmin" 1 +@@ -1339,14 +1337,14 @@ (define_insn_reservation "c86_4g_m7_sse_sseadd_maxmin_load" 8 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu2|c86-4g-m7-fpu3") + + ;; SUB/ADD +-(define_insn_reservation "c86_4g_m7_avx512_sseadd_xy" 3 ++(define_insn_reservation "c86_4g_m7_avx512_sseadd" 3 + (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "type" "sseadd") + (and (eq_attr "c86_attr" "other") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-fpu_1_3") + +-(define_insn_reservation "c86_4g_m7_avx512_sseadd_xy_load" 10 ++(define_insn_reservation "c86_4g_m7_avx512_sseadd_load" 10 + (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "type" "sseadd") + (and (eq_attr "c86_attr" "other") +@@ -1411,7 +1409,7 @@ (define_insn_reservation "c86_4g_m7_sse_sseiadd_sadbw" 3 + (and (eq_attr "c86_attr" "sadbw") + (and (eq_attr "prefix" "orig") + (eq_attr "memory" "none"))))) +- "c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu3") ++ "c86-4g-m7-direct,c86-4g-m7-fpu_0_3") + + (define_insn_reservation "c86_4g_m7_sse_sseiadd_sadbw_mem" 10 + (and (eq_attr "cpu" "c86_4g_m7") +@@ -1419,7 +1417,7 @@ (define_insn_reservation "c86_4g_m7_sse_sseiadd_sadbw_mem" 10 + (and (eq_attr "c86_attr" "sadbw") + (and (eq_attr "prefix" "orig") + (eq_attr "memory" "load"))))) +- "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu3") ++ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_3") + + (define_insn_reservation "c86_4g_m7_sse_sseiadd_madd" 3 + (and (eq_attr "cpu" "c86_4g_m7") +@@ -1598,7 +1596,7 @@ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_z" 5 + (and (eq_attr "mode" "XI") + (and (eq_attr "c86_attr" "other,ptest") + (eq_attr "memory" "none")))))) +- "c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3") ++ "c86-4g-m7-vector,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_z_load" 12 + (and (eq_attr "cpu" "c86_4g_m7") +@@ -1607,7 +1605,7 @@ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_z_load" 12 + (and (eq_attr "mode" "XI") + (and (eq_attr "c86_attr" "other,ptest") + (eq_attr "memory" "load")))))) +- "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3x2") ++ "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3x2") + + (define_insn_reservation "c86_4g_m7_avx_ssecmp_vp" 1 + (and (eq_attr "cpu" "c86_4g_m7") +@@ -1638,7 +1636,7 @@ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_test_load" 13 + (and (eq_attr "mode" "TI,OI") + (and (eq_attr "c86_attr" "ptest") + (eq_attr "memory" "load"))))) +- "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1,c86-4g-m7-fpu_1_3") ++ "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3") + + ;; SSECVT + (define_insn_reservation "c86_4g_m7_avx512_ssecvt_xy" 4 +@@ -2042,7 +2040,7 @@ (define_insn_reservation "c86_4g_m7_avx512_mskmov_k_reg" 3 + (match_operand 1 "register_operand" "r")))) + "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_1_3") + +-(define_insn_reservation "c86_4g_m7_avx512_mskmov_k_m" 8 ++(define_insn_reservation "c86_4g_m7_avx512_mskmov_k_m" 9 + (and (eq_attr "cpu" "c86_4g_m7") + (and (eq_attr "type" "mskmov") + (and (match_operand 0 "register_operand" "k") +-- +2.34.1 + diff --git a/HYGON-0005-i386-Adjust-c86-4g-m7-512-bit-memory-costs.patch b/HYGON-0005-i386-Adjust-c86-4g-m7-512-bit-memory-costs.patch new file mode 100644 index 0000000000000000000000000000000000000000..1c8f3ef6ac5b262e66e6defa1d001010ca41a17b --- /dev/null +++ b/HYGON-0005-i386-Adjust-c86-4g-m7-512-bit-memory-costs.patch @@ -0,0 +1,65 @@ +From 5cef336c48384d881c7f770a544e36ef01daebd3 Mon Sep 17 00:00:00 2001 +From: Zhongjie Guo +Date: Wed, 17 Jun 2026 03:29:15 +0000 +Subject: [PATCH 2/3] i386: Adjust c86-4g-m7 512-bit memory costs + +c86-4g-m7 is a split-regs AVX512 target. A 512-bit memory +operation is implemented as two 256-bit halves, so model 512-bit +memory accesses with twice the 256-bit load/store cost. + +This keeps the c86_4g_m7_cost vectorizer memory cost model aligned +with the target architecture instead of treating 512-bit loads and +stores as almost the same cost as 256-bit operations. + +gcc/ChangeLog: + + * config/i386/x86-tune-costs.h (c86_4g_m7_cost): Increase + 512-bit load/store and unaligned load/store costs. + +Signed-off-by: Zhongjie Guo +--- + gcc/config/i386/x86-tune-costs.h | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h +index d2cc3ff2f47..00caf8ebde5 100644 +--- a/gcc/config/i386/x86-tune-costs.h ++++ b/gcc/config/i386/x86-tune-costs.h +@@ -1848,9 +1848,9 @@ struct processor_costs znver4_cost = { + in SImode and DImode. */ + 2, 2, 3, /* cost of moving XMM,YMM,ZMM + register. */ +- {6, 6, 10, 10, 12}, /* cost of loading SSE registers ++ {6, 6, 10, 10, 20}, /* cost of loading SSE registers + in 32,64,128,256 and 512-bit. */ +- {8, 8, 8, 12, 12}, /* cost of storing SSE registers ++ {8, 8, 8, 12, 24}, /* cost of storing SSE registers + in 32,64,128,256 and 512-bit. */ + 6, 8, /* SSE->integer and integer->SSE + moves. */ +@@ -1890,9 +1890,9 @@ struct processor_costs znver4_cost = { + Relative to reg-reg move (2). */ + {8, 8, 8}, /* cost of storing integer + registers. */ +- {6, 6, 10, 10, 12}, /* cost of loading SSE registers ++ {6, 6, 10, 10, 20}, /* cost of loading SSE registers + in 32bit, 64bit, 128bit, 256bit and 512bit */ +- {8, 8, 8, 12, 12}, /* cost of storing SSE register ++ {8, 8, 8, 12, 24}, /* cost of storing SSE register + in 32bit, 64bit, 128bit, 256bit and 512bit */ + {6, 6, 6, 6, 6}, /* cost of unaligned loads. */ + {8, 8, 8, 8, 8}, /* cost of unaligned stores. */ +@@ -4038,8 +4038,8 @@ struct processor_costs c86_4g_m7_cost = { + {8, 8, 8, 12, 12}, /* cost of storing SSE register + in 32bit, 64bit, 128bit, 256bit and + 512bit. */ +- {6, 6, 10, 10, 12}, /* cost of unaligned loads. */ +- {8, 8, 8, 12, 12}, /* cost of unaligned stores. */ ++ {6, 6, 10, 10, 20}, /* cost of unaligned loads. */ ++ {8, 8, 8, 12, 24}, /* cost of unaligned stores. */ + 2, 2, 3, /* cost of moving XMM,YMM,ZMM + register. */ + 6, /* cost of moving SSE register to +-- +2.34.1 + diff --git a/HYGON-0006-i386-Add-HYGON-c86-4g-m8-support.patch b/HYGON-0006-i386-Add-HYGON-c86-4g-m8-support.patch new file mode 100644 index 0000000000000000000000000000000000000000..2cf061db30871d152de9565459102c7478d10eb7 --- /dev/null +++ b/HYGON-0006-i386-Add-HYGON-c86-4g-m8-support.patch @@ -0,0 +1,2881 @@ +From 66b2f96cfedb7e6973ad30f39ab11513c6415dad Mon Sep 17 00:00:00 2001 +From: Xin Liu +Date: Wed, 1 Jul 2026 11:32:13 +0000 +Subject: [PATCH 3/3] i386: Add HYGON c86-4g-m8 support + +Add c86-4g-m8 as a new HYGON Family 18h model 8 processor. It +inherits the c86-4g-m7 ISA set and most tuning decisions, including +the same processor costs and scheduling model baseline. + +The patch wires c86-4g-m8 into the common x86 processor tables, +driver CPU detection, target macros, --with-arch/--with-cpu handling, +builtin CPU detection and documentation. It also extends the c86-4g +tuning masks that already special-case c86-4g-m7 to cover c86-4g-m8. + +For scheduling, rename the shared scheduling description file from +gcc/config/i386/c86-4g-m7.md to gcc/config/i386/c86-4g-m7m8.md and +reuse the c86-4g-m7 scheduling reservations for c86-4g-m8 where the +latency and resource usage are the same. Add separate c86-4g-m8 +reservations for the few operations with different latency. This patch +does not affect genautomata build time. + +gcc/ChangeLog: + + * common/config/i386/cpuinfo.h (get_hygon_cpu): Detect HYGON + Family 18h model 8 as c86-4g-m8. + * common/config/i386/i386-common.cc (processor_names): Add + c86-4g-m8. + (processor_alias_table): Likewise. + * common/config/i386/i386-cpuinfo.h (enum processor_subtypes): Add + HYGONFAM18H_C86_4G_M8. + * config.gcc: Add c86-4g-m8 to supported x86 CPUs and handle + c86_4g_m8 target triples. + * config/i386/c86-4g-m7.md: Rename to ... + * config/i386/c86-4g-m7m8.md: ... this and extend shared c86-4g-m7 + scheduling reservations to c86-4g-m8. + (c86_4g_m8_imovx_cwde): New reservation. + (c86_4g_m7_imov_xchg): Add c86_4g_m8 to CPU attribute. + (c86_4g_m7_imov_xchg_load): Ditto. + (c86_4g_m7_imov): Ditto. + (c86_4g_m7_imov_load): Ditto. + (c86_4g_m7_imov_store): Ditto. + (c86_4g_m7_push): Ditto. + (c86_4g_m7_push_mem): Ditto. + (c86_4g_m7_pop): Ditto. + (c86_4g_m7_pop_mem): Ditto. + (c86_4g_m7_imul): Ditto. + (c86_4g_m7_imul_load): Ditto. + (c86_4g_m7_idiv): Ditto. + (c86_4g_m7_idiv_QI): Ditto. + (c86_4g_m7_idiv_load): Ditto. + (c86_4g_m7_idiv_QI_load): Ditto. + (c86_4g_m7_insn): Ditto. + (c86_4g_m7_insn_load): Ditto. + (c86_4g_m7_insn_store): Ditto. + (c86_4g_m7_insn2_store): Ditto. + (c86_4g_m7_insn_both): Ditto. + (c86_4g_m7_setcc): Ditto. + (c86_4g_m7_setcc_load): Ditto. + (c86_4g_m7_setcc_store): Ditto. + (c86_4g_m7_alu1_double): Ditto. + (c86_4g_m7_alu1_double_load): Ditto. + (c86_4g_m7_alu1_vector): Ditto. + (c86_4g_m7_alu1_vector_load): Ditto. + (c86_4g_m7_alu1_direct): Ditto. + (c86_4g_m7_alu1_direct_load): Ditto. + (c86_4g_m7_call): Ditto. + (c86_4g_m7_branch): Ditto. + (c86_4g_m7_branch_load): Ditto. + (c86_4g_m7_lea): Ditto. + (c86_4g_m7_leave): Ditto. + (c86_4g_m7_str): Ditto. + (c86_4g_m7_str_load): Ditto. + (c86_4g_m7_ieu_vector): Ditto. + (c86_4g_m7_ieu_vector_load): Ditto. + (c86_4g_m7_sse_insertimm): Ditto. + (c86_4g_m7_sse_insert): Ditto. + (c86_4g_m7_fp_cmov): Ditto. + (c86_4g_m7_fp_mov_direct_load): Ditto. + (c86_4g_m7_fp_mov_direct_store): Ditto. + (c86_4g_m7_fp_mov_double_load): Ditto. + (c86_4g_m7_fp_mov_double_store): Ditto. + (c86_4g_m7_fp_mov_direct): Ditto. + (c86_4g_m7_fp_sqrt): Ditto. + (c86_4g_m7_fp_spc_direct): Ditto. + (c86_4g_m7_fp_spc): Ditto. + (c86_4g_m7_fp_op_mul): Ditto. + (c86_4g_m7_fp_op_mul_load): Ditto. + (c86_4g_m7_fp_op_imul_load): Ditto. + (c86_4g_m7_fp_div): Ditto. + (c86_4g_m7_fp_div_load): Ditto. + (c86_4g_m7_fp_idiv_load): Ditto. + (c86_4g_m7_fp_fsgn): Ditto. + (c86_4g_m7_fp_fcmp): Ditto. + (c86_4g_m7_fp_fcmp_load): Ditto. + (c86_4g_m7_fp_mmx): Ditto. + (c86_4g_m7_mmx_add_cmp): Ditto. + (c86_4g_m7_mmx_add_cmp_load): Ditto. + (c86_4g_m7_mmx_cvt): Ditto. + (c86_4g_m7_mmx_cvt_load): Ditto. + (c86_4g_m7_mmx_shift): Ditto. + (c86_4g_m7_mmx_shift_load): Ditto. + (c86_4g_m7_mmx_shift_avg): Ditto. + (c86_4g_m7_mmx_shift_avg_load): Ditto. + (c86_4g_m7_mmx_shift_sadbw): Ditto. + (c86_4g_m7_mmx_shift_sadbw_load): Ditto. + (c86_4g_m7_mmx_mov): Ditto. + (c86_4g_m7_mmx_mov_store): Ditto. + (c86_4g_m7_mmx_mov_load): Ditto. + (c86_4g_m7_mmx_mul): Ditto. + (c86_4g_m7_mmx_mul_load): Ditto. + (c86_4g_m7_sse_pinsr_reg): Ditto. + (c86_4g_m7_sse_pinsr_reg_load): Ditto. + (c86_4g_m7_avx_vpinsr_reg): Ditto. + (c86_4g_m7_avx_vpinsr_reg_load): Ditto. + (c86_4g_m7_avx512_perm_xmm): Ditto. + (c86_4g_m7_avx512_perm_xmm_opload): Ditto. + (c86_4g_m7_avx512_permi2_ymm): Ditto. + (c86_4g_m7_avx512_permi2_zmm): Ditto. + (c86_4g_m7_avx512_permi2_ymm_load): Ditto. + (c86_4g_m7_avx512_permi2_zmm_load): Ditto. + (c86_4g_m7_avx512_perm_zmm_imm): Ditto. + (c86_4g_m7_avx512_perm_zmm_imm_load): Ditto. + (c86_4g_m7_avx512_perm_zmm_noimm): Ditto. + (c86_4g_m7_sse_perm_zmm_noimm_load): Ditto. + (c86_4g_m7_avx512_insertx_ymm): Ditto. + (c86_4g_m7_avx512_insertx_ymem): Ditto. + (c86_4g_m7_avx512_insertx_zxmm): Ditto. + (c86_4g_m7_avx512_insertx_zxmem): Ditto. + (c86_4g_m7_avx512_insertx_zymm): Ditto. + (c86_4g_m7_avx512_insertx_zymem): Ditto. + (c86_4g_m7_avx_insertx_ymm): Ditto. + (c86_4g_m7_avx_insertx_ymem): Ditto. + (c86_4g_m7_avx512_shuf_xymm): Ditto. + (c86_4g_m7_avx512_shuf_zmm): Ditto. + (c86_4g_m7_avx512_shuf_xymem): Ditto. + (c86_4g_m7_avx512_shuf_zmem): Ditto. + (c86_4g_m7_sselogic_xymm): Ditto. + (c86_4g_m7_sselogic_xymm_load): Ditto. + (c86_4g_m7_avx512_cmpestr): Ditto. + (c86_4g_m7_avx512_cmpestr_load): Ditto. + (c86_4g_m7_avx512_log): Ditto. + (c86_4g_m7_avx512_log_load): Ditto. + (c86_4g_m7_avx512_vdbpsadbw_xymm): Ditto. + (c86_4g_m7_avx512_vdbpsadbw_xymem): Ditto. + (c86_4g_m7_avx512_vdbpsadbw_zmm): Ditto. + (c86_4g_m7_avx512_vdbpsadbw_zmem): Ditto. + (c86_4g_m7_avx512_abs): Ditto. + (c86_4g_m7_avx512_abs_load): Ditto. + (c86_4g_m7_avx_sign): Ditto. + (c86_4g_m7_avx_sign_load): Ditto. + (c86_4g_m7_avx_blend): Ditto. + (c86_4g_m7_avx_blend_load): Ditto. + (c86_4g_m7_avx512_aes): Ditto. + (c86_4g_m7_avx512_aes_load): Ditto. + (c86_4g_m7_avx_aes): Ditto. + (c86_4g_m7_avx_aes_load): Ditto. + (c86_4g_m7_extr): Ditto. + (c86_4g_m7_extr_store): Ditto. + (c86_4g_m7_avx_ssecomi_comi): Ditto. + (c86_4g_m7_avx_ssecomi_comi_load): Ditto. + (c86_4g_m7_avx_ssecomi_test): Ditto. + (c86_4g_m7_avx_ssecomi_test_load): Ditto. + (c86_4g_m7_avx512_imul): Ditto. + (c86_4g_m7_avx512_imul_mem): Ditto. + (c86_4g_m7_avx_imul): Ditto. + (c86_4g_m7_avx_imul_mem): Ditto. + (c86_4g_m7_avx512_mov_vmov): Ditto. + (c86_4g_m7_avx512_mov_vmov_store): Ditto. + (c86_4g_m7_avx512_mov_vmov_load): Ditto. + (c86_4g_m7_avx512_vpmovx_y): Ditto. + (c86_4g_m7_avx512_vpmovx_y_load): Ditto. + (c86_4g_m7_avx512_vpmovx_z): Ditto. + (c86_4g_m7_avx512_vpmovx_z_load): Ditto. + (c86_4g_m7_avx512_vpmovx_x): Ditto. + (c86_4g_m7_avx512_vpmovx_x_load): Ditto. + (c86_4g_m7_avx_vpmovx_xx): Ditto. + (c86_4g_m7_avx_vpmovx_xx_load): Ditto. + (c86_4g_m7_avx512_expand): Ditto. + (c86_4g_m7_avx512_expand_load): Ditto. + (c86_4g_m7_avx512_expand_z): Ditto. + (c86_4g_m7_avx512_expand_z_load): Ditto. + (c86_4g_m7_avx512_movnt_load): Ditto. + (c86_4g_m7_avx512_movnt_store): Ditto. + (c86_4g_m7_sse_movnt_store): Ditto. + (c86_4g_m7_sse_movnt): Ditto. + (c86_4g_m7_avx512_blendv): Ditto. + (c86_4g_m7_avx512_blendv_load): Ditto. + (c86_4g_m7_sse_mov2): Ditto. + (c86_4g_m7_sse_mov2_load): Ditto. + (c86_4g_m7_avx512_sseishft_aligr): Ditto. + (c86_4g_m7_avx512_sseishft_aligr_load): Ditto. + (c86_4g_m7_avx512_sseishft_vshift): Ditto. + (c86_4g_m7_avx512_sseishft_vshift_load): Ditto. + (c86_4g_m7_avx512_sseadd_maxmin): Ditto. + (c86_4g_m7_avx512_sseadd_maxmin_load): Ditto. + (c86_4g_m7_avx_sseadd_maxmin): Ditto. + (c86_4g_m7_avx_sseadd_maxmin_load): Ditto. + (c86_4g_m7_sse_sseadd_maxmin): Ditto. + (c86_4g_m7_sse_sseadd_maxmin_load): Ditto. + (c86_4g_m7_avx512_sseadd): Ditto. + (c86_4g_m7_avx512_sseadd_load): Ditto. + (c86_4g_m7_avx_sseadd_hplus): Ditto. + (c86_4g_m7_avx_sseadd_hplus_load): Ditto. + (c86_4g_m7_avx512_sseiadd_madd): Ditto. + (c86_4g_m7_avx512_sseiadd_madd_mem): Ditto. + (c86_4g_m7_avx_sseiadd_sadbw): Ditto. + (c86_4g_m7_avx_sseiadd_sadbw_mem): Ditto. + (c86_4g_m7_sse_sseiadd_sadbw): Ditto. + (c86_4g_m7_sse_sseiadd_sadbw_mem): Ditto. + (c86_4g_m7_sse_sseiadd_madd): Ditto. + (c86_4g_m7_sse_sseiadd_madd_mem): Ditto. + (c86_4g_m7_avx512_sseiadd_avg): Ditto. + (c86_4g_m7_avx512_sseiadd_avg_load): Ditto. + (c86_4g_m7_avx_sseiadd_hplus): Ditto. + (c86_4g_m7_avx_sseiadd_hplus_load): Ditto. + (c86_4g_m7_sse_sseiadd_hplus): Ditto. + (c86_4g_m7_sse_sseiadd_hplus_load): Ditto. + (c86_4g_m8_avx512_ssemul): New reservation. + (c86_4g_m8_avx512_ssemul_load): Ditto. + (c86_4g_m7_avx512_ssediv_x): Add c86_4g_m8 to CPU attribute. + (c86_4g_m7_avx512_ssediv_xmem): Ditto. + (c86_4g_m7_avx512_ssediv_y): Ditto. + (c86_4g_m7_avx512_ssediv_ymem): Ditto. + (c86_4g_m7_avx512_ssediv_z): Ditto. + (c86_4g_m7_avx512_ssediv_zmem): Ditto. + (c86_4g_m7_avx512_ssecmp): Ditto. + (c86_4g_m7_avx512_ssecmp_load): Ditto. + (c86_4g_m7_avx512_ssecmp_z): Ditto. + (c86_4g_m7_avx512_ssecmp_z_load): Ditto. + (c86_4g_m7_avx512_ssecmp_vp): Ditto. + (c86_4g_m7_avx512_ssecmp_vp_load): Ditto. + (c86_4g_m7_avx512_ssecmp_vp_z): Ditto. + (c86_4g_m7_avx512_ssecmp_vp_z_load): Ditto. + (c86_4g_m7_avx_ssecmp_vp): Ditto. + (c86_4g_m7_avx_ssecmp_vp_load): Ditto. + (c86_4g_m7_avx512_ssecmp_test): Ditto. + (c86_4g_m7_avx512_ssecmp_test_load): Ditto. + (c86_4g_m7_avx512_ssecvt_xy): Ditto. + (c86_4g_m7_avx512_ssecvt_xy_load): Ditto. + (c86_4g_m7_avx512_ssecvt_y_z): Ditto. + (c86_4g_m7_avx512_ssecvt_y_z_load): Ditto. + (c86_4g_m7_avx512_ssecvt_z): Ditto. + (c86_4g_m7_avx512_ssecvt_z_load): Ditto. + (c86_4g_m7_avx_ssecvt): Ditto. + (c86_4g_m7_avx_ssecvt_load): Ditto. + (c86_4g_m7_sse_ssecvt_pspi): Ditto. + (c86_4g_m7_sse_ssecvt_pspi_load): Ditto. + (c86_4g_m7_sse_ssecvt_pi): Ditto. + (c86_4g_m7_sse_ssecvt_pi_load): Ditto. + (c86_4g_m8_avx512_muladd): New reservation. + (c86_4g_m8_avx512_muladd_load): Ditto. + (c86_4g_m7_avx512_muladd_madd): Add c86_4g_m8 to CPU attribute. + (c86_4g_m7_avx512_muladd_madd_load): Ditto. + (c86_4g_m7_avx512_sse_range): Ditto. + (c86_4g_m7_avx512_sse_range_load): Ditto. + (c86_4g_m7_avx512_sse_conflict_x): Ditto. + (c86_4g_m7_avx512_sse_conflict_x_load): Ditto. + (c86_4g_m7_avx512_sse_conflict_y): Ditto. + (c86_4g_m7_avx512_sse_conflict_y_load): Ditto. + (c86_4g_m7_avx512_sse_conflict_z): Ditto. + (c86_4g_m7_avx512_sse_conflict_z_load): Ditto. + (c86_4g_m7_avx512_sse_class): Ditto. + (c86_4g_m7_avx512_sse_class_load): Ditto. + (c86_4g_m7_avx512_sse_class_z): Ditto. + (c86_4g_m7_avx512_sse_class_z_load): Ditto. + (c86_4g_m7_avx_sse): Ditto. + (c86_4g_m7_avx_sse_load): Ditto. + (c86_4g_m7_avx512_sse_sqrt_sf_x): Ditto. + (c86_4g_m7_avx512_sse_sqrt_sf_xload): Ditto. + (c86_4g_m7_avx512_sse_sqrt_sf_y): Ditto. + (c86_4g_m7_avx512_sse_sqrt_sf_yload): Ditto. + (c86_4g_m7_avx512_sse_sqrt_sf_z): Ditto. + (c86_4g_m7_avx512_sse_sqrt_sf_zload): Ditto. + (c86_4g_m7_avx512_sse_sqrt_df_x): Ditto. + (c86_4g_m7_avx512_sse_sqrt_df_xload): Ditto. + (c86_4g_m7_avx512_sse_sqrt_df_y): Ditto. + (c86_4g_m7_avx512_sse_sqrt_df_yload): Ditto. + (c86_4g_m7_avx512_sse_sqrt_df_z): Ditto. + (c86_4g_m7_avx512_sse_sqrt_df_zload): Ditto. + (c86_4g_m7_avx512_msklog): Ditto. + (c86_4g_m7_avx512_msklog_vector): Ditto. + (c86_4g_m7_avx512_mskmov_reg_k): Ditto. + (c86_4g_m7_avx512_mskmov_xy_k): Ditto. + (c86_4g_m7_avx512_mskmov_z_k): Ditto. + (c86_4g_m7_avx512_mskmov_k_k): Ditto. + (c86_4g_m7_avx512_mskmov_k_reg): Ditto. + (c86_4g_m7_avx512_mskmov_k_m): Ditto. + * config/i386/driver-i386.cc (host_detect_local_cpu): Detect + c86-4g-m8. + * config/i386/i386-c.cc (ix86_target_macros_internal): Define + c86-4g-m8 arch and tune macros. + * config/i386/i386-options.cc (m_C86_4G_M8): New macro. + (m_C86_4G): Include m_C86_4G_M8. + (processor_cost_table): Add c86_4g_m8_cost. + * config/i386/i386.cc (ix86_reassociation_width): Handle + PROCESSOR_C86_4G_M8. + * config/i386/i386.h (enum processor_type): Add + PROCESSOR_C86_4G_M8. + (PTA_C86_4G_M8): New. + * config/i386/i386.md: Add c86_4g_m8 to cpu attribute and include + c86-4g-m7m8.md. + * config/i386/x86-tune-costs.h (c86_4g_m8_cost): New. + * config/i386/x86-tune-sched.cc (ix86_issue_rate): Handle + PROCESSOR_C86_4G_M8. + (ix86_adjust_cost): Likewise. + * config/i386/x86-tune.def (X86_TUNE_USE_SCATTER_2PARTS): Include + m_C86_4G_M8. + (X86_TUNE_USE_SCATTER_4PARTS): Likewise. + (X86_TUNE_USE_SCATTER_8PARTS): Likewise. + (X86_TUNE_AVX512_SPLIT_REGS): Likewise. + (X86_TUNE_AVX512_MOVE_BY_PIECES): Likewise. + (X86_TUNE_AVX512_STORE_BY_PIECES): Likewise. + * doc/extend.texi: Document c86-4g-m8 for __builtin_cpu_is. + * doc/invoke.texi: Document c86-4g-m8. + +gcc/testsuite/ChangeLog: + + * g++.target/i386/mv33.C: Add c86-4g-m8 target clone test. + * gcc.target/i386/funcspec-56.inc: Add c86-4g-m8 arch and tune + target attribute tests. + +Signed-off-by: Xin Liu +--- + gcc/common/config/i386/cpuinfo.h | 6 + + gcc/common/config/i386/i386-common.cc | 6 +- + gcc/common/config/i386/i386-cpuinfo.h | 1 + + gcc/config.gcc | 10 +- + .../i386/{c86-4g-m7.md => c86-4g-m7m8.md} | 540 ++++++++++-------- + gcc/config/i386/driver-i386.cc | 7 +- + gcc/config/i386/i386-c.cc | 7 + + gcc/config/i386/i386-options.cc | 7 +- + gcc/config/i386/i386.cc | 3 +- + gcc/config/i386/i386.h | 2 + + gcc/config/i386/i386.md | 4 +- + gcc/config/i386/x86-tune-costs.h | 2 + + gcc/config/i386/x86-tune-sched.cc | 3 +- + gcc/config/i386/x86-tune.def | 12 +- + gcc/doc/extend.texi | 3 + + gcc/doc/invoke.texi | 9 + + gcc/testsuite/g++.target/i386/mv33.C | 6 + + gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 + + 18 files changed, 363 insertions(+), 267 deletions(-) + rename gcc/config/i386/{c86-4g-m7.md => c86-4g-m7m8.md} (84%) + +diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h +index 9ec5d9f4750..b682a412d2b 100644 +--- a/gcc/common/config/i386/cpuinfo.h ++++ b/gcc/common/config/i386/cpuinfo.h +@@ -349,6 +349,12 @@ get_hygon_cpu (struct __processor_model *cpu_model, + CHECK___builtin_cpu_is ("c86-4g-m7"); + cpu_model->__cpu_subtype = HYGONFAM18H_C86_4G_M7; + } ++ else if (model == 0x8) ++ { ++ cpu = "c86-4g-m8"; ++ CHECK___builtin_cpu_is ("c86-4g-m8"); ++ cpu_model->__cpu_subtype = HYGONFAM18H_C86_4G_M8; ++ } + break; + default: + break; +diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc +index e2877e0d547..edcb87d7798 100644 +--- a/gcc/common/config/i386/i386-common.cc ++++ b/gcc/common/config/i386/i386-common.cc +@@ -1837,7 +1837,8 @@ const char *const processor_names[] = + "znver4", + "c86-4g-m4", + "c86-4g-m6", +- "c86-4g-m7" ++ "c86-4g-m7", ++ "c86-4g-m8" + }; + + /* Guarantee that the array is aligned with enum processor_type. */ +@@ -2103,6 +2104,9 @@ const pta processor_alias_table[] = + {"c86-4g-m7", PROCESSOR_C86_4G_M7, CPU_C86_4G_M7, + PTA_C86_4G_M7, + M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M7), P_PROC_AVX512F}, ++ {"c86-4g-m8", PROCESSOR_C86_4G_M8, CPU_C86_4G_M8, ++ PTA_C86_4G_M8, ++ M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M8), P_PROC_AVX512F}, + + {"generic", PROCESSOR_GENERIC, CPU_GENERIC, + PTA_64BIT +diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h +index 99254b72e1b..7b15b537b21 100644 +--- a/gcc/common/config/i386/i386-cpuinfo.h ++++ b/gcc/common/config/i386/i386-cpuinfo.h +@@ -102,6 +102,7 @@ enum processor_subtypes + HYGONFAM18H_C86_4G_M4, + HYGONFAM18H_C86_4G_M6, + HYGONFAM18H_C86_4G_M7, ++ HYGONFAM18H_C86_4G_M8, + CPU_SUBTYPE_MAX + }; + +diff --git a/gcc/config.gcc b/gcc/config.gcc +index 35641a74d68..f72a7d499a0 100644 +--- a/gcc/config.gcc ++++ b/gcc/config.gcc +@@ -672,7 +672,7 @@ silvermont knl knm skylake-avx512 cannonlake icelake-client icelake-server \ + skylake goldmont goldmont-plus tremont cascadelake tigerlake cooperlake \ + sapphirerapids alderlake rocketlake eden-x2 nano nano-1000 nano-2000 nano-3000 \ + nano-x2 eden-x4 nano-x4 x86-64 x86-64-v2 x86-64-v3 x86-64-v4 lujiazui yongfeng \ +-shijidadao c86-4g-m4 c86-4g-m6 c86-4g-m7 native" ++shijidadao c86-4g-m4 c86-4g-m6 c86-4g-m7 c86-4g-m8 native" + + # Additional x86 processors supported by --with-cpu=. Each processor + # MUST be separated by exactly one space. +@@ -3889,6 +3889,10 @@ case ${target} in + arch=c86-4g-m7 + cpu=c86-4g-m7 + ;; ++ c86_4g_m8-*) ++ arch=c86-4g-m8 ++ cpu=c86-4g-m8 ++ ;; + *) + arch=pentiumpro + cpu=generic +@@ -3995,6 +3999,10 @@ case ${target} in + arch=c86-4g-m7 + cpu=c86-4g-m7 + ;; ++ c86_4g_m8-*) ++ arch=c86-4g-m8 ++ cpu=c86-4g-m8 ++ ;; + *) + arch=x86-64 + cpu=generic +diff --git a/gcc/config/i386/c86-4g-m7.md b/gcc/config/i386/c86-4g-m7m8.md +similarity index 84% +rename from gcc/config/i386/c86-4g-m7.md +rename to gcc/config/i386/c86-4g-m7m8.md +index 8c784a145bf..31d083cfa1d 100644 +--- a/gcc/config/i386/c86-4g-m7.md ++++ b/gcc/config/i386/c86-4g-m7m8.md +@@ -17,7 +17,7 @@ + ;; . + ;; + +-;; HYGON c86-4g-m7 Scheduling ++;; HYGON c86-4g-m7/m8 Scheduling + ;; Modeling automatons for decoders, integer execution pipes, + ;; AGU pipes, branch, floating point execution, fp store units, + ;; integer and floating point dividers. Split fpu1 and fpu3 +@@ -112,15 +112,18 @@ (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x15" "(c86-4g-m7-fp1fdiv1x4,c86 + (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x18" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*18)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*18)") + + ;; IMOV/IMOVX ++ ++;; Some reservations keep the historical "m7" naming, while their CPU ++;; attributes include both m7 and m8. + (define_insn_reservation "c86_4g_m7_imov_xchg" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "imov") + (and (eq_attr "c86_decode" "vector") + (eq_attr "memory" "none")))) + "c86-4g-m7-vector") + + (define_insn_reservation "c86_4g_m7_imov_xchg_load" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "imov") + (and (eq_attr "c86_decode" "vector") + (eq_attr "memory" "!none")))) +@@ -133,22 +136,29 @@ (define_insn_reservation "c86_4g_m7_imovx_cwde" 2 + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-ieu") + ++(define_insn_reservation "c86_4g_m8_imovx_cwde" 1 ++ (and (eq_attr "cpu" "c86_4g_m8") ++ (and (eq_attr "type" "imovx") ++ (and (eq_attr "c86_decode" "double") ++ (eq_attr "memory" "none")))) ++ "c86-4g-m7-direct,c86-4g-m7-ieu") ++ + (define_insn_reservation "c86_4g_m7_imov" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "imov,imovx") + (and (eq_attr "c86_decode" "direct") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-ieu") + + (define_insn_reservation "c86_4g_m7_imov_load" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "imov,imovx") + (and (eq_attr "c86_decode" "!vector") + (eq_attr "memory" "load")))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu") + + (define_insn_reservation "c86_4g_m7_imov_store" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "imov,imovx") + (and (eq_attr "c86_decode" "!vector") + (eq_attr "memory" "store")))) +@@ -156,67 +166,67 @@ (define_insn_reservation "c86_4g_m7_imov_store" 1 + + ;; PUSH + (define_insn_reservation "c86_4g_m7_push" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "push,sse") + (eq_attr "memory" "store"))) + "c86-4g-m7-direct,c86-4g-m7-store") + + (define_insn_reservation "c86_4g_m7_push_mem" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "push") + (eq_attr "memory" "both"))) + "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-store") + + ;; POP + (define_insn_reservation "c86_4g_m7_pop" 4 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "pop") + (eq_attr "memory" "load"))) + "c86-4g-m7-direct,c86-4g-m7-load") + + (define_insn_reservation "c86_4g_m7_pop_mem" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "pop") + (eq_attr "memory" "both"))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store") + + ;; IMUL/IMULX + (define_insn_reservation "c86_4g_m7_imul" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "imul,imulx") + (eq_attr "memory" "none"))) + "c86-4g-m7-direct,c86-4g-m7-ieu1") + + (define_insn_reservation "c86_4g_m7_imul_load" 7 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "imul") + (eq_attr "memory" "!none"))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu1") + + ;; IDIV + (define_insn_reservation "c86_4g_m7_idiv" 7 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "idiv") + (and (eq_attr "mode" "!QI") + (eq_attr "memory" "none")))) + "c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*7") + + (define_insn_reservation "c86_4g_m7_idiv_QI" 6 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "idiv") + (and (eq_attr "mode" "QI") + (eq_attr "memory" "none")))) + "c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*6") + + (define_insn_reservation "c86_4g_m7_idiv_load" 11 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "idiv") + (and (eq_attr "mode" "!QI") + (eq_attr "memory" "load")))) + "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*7") + + (define_insn_reservation "c86_4g_m7_idiv_QI_load" 10 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "idiv") + (and (eq_attr "mode" "QI") + (eq_attr "memory" "load")))) +@@ -224,95 +234,95 @@ (define_insn_reservation "c86_4g_m7_idiv_QI_load" 10 + + ;; Integer/genaral Instructions + (define_insn_reservation "c86_4g_m7_insn" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "alu,negnot,rotate1,ishift1,test,incdec,icmp, + rotate,rotatex,ishift,ishiftx,icmov") + (eq_attr "memory" "none,unknown"))) + "c86-4g-m7-direct,c86-4g-m7-ieu") + + (define_insn_reservation "c86_4g_m7_insn_load" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "alu,incdec,icmp,test,ishift, + ishiftx,icmov,rotate,rotatex") + (eq_attr "memory" "load"))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu") + + (define_insn_reservation "c86_4g_m7_insn_store" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ishift1,rotate1,rotate,incdec, + alu,icmov,ishift,negnot,alu1") + (eq_attr "memory" "store"))) + "c86-4g-m7-direct,c86-4g-m7-ieu,c86-4g-m7-store") + + (define_insn_reservation "c86_4g_m7_insn2_store" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "icmp") + (eq_attr "memory" "store"))) + "c86-4g-m7-direct,c86-4g-m7-ieu,c86-4g-m7-store") + + (define_insn_reservation "c86_4g_m7_insn_both" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "alu,negnot,rotate1,ishift1,incdec,rotate, + rotatex,ishift,ishiftx,icmov") + (eq_attr "memory" "both"))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu,c86-4g-m7-store") + + (define_insn_reservation "c86_4g_m7_setcc" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "setcc") + (eq_attr "memory" "none,unknown"))) + "c86-4g-m7-direct,c86-4g-m7-ieu0|c86-4g-m7-ieu3") + + (define_insn_reservation "c86_4g_m7_setcc_load" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "setcc") + (eq_attr "memory" "load"))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu0|c86-4g-m7-ieu3") + + (define_insn_reservation "c86_4g_m7_setcc_store" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "setcc") + (eq_attr "memory" "store"))) + "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-ieu0|c86-4g-m7-ieu3") + + ;; ALU1 + (define_insn_reservation "c86_4g_m7_alu1_double" 2 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "alu1") + (and (eq_attr "c86_decode" "double") + (eq_attr "memory" "none,unknown")))) + "c86-4g-m7-double,c86-4g-m7-ieu") + + (define_insn_reservation "c86_4g_m7_alu1_double_load" 6 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "alu1") + (and (eq_attr "c86_decode" "double") + (eq_attr "memory" "both")))) + "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ieu") + + (define_insn_reservation "c86_4g_m7_alu1_vector" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "alu1") + (and (eq_attr "c86_decode" "vector") + (eq_attr "memory" "none,unknown")))) + "c86-4g-m7-vector,c86-4g-m7-ivector*3") + + (define_insn_reservation "c86_4g_m7_alu1_vector_load" 7 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "alu1") + (and (eq_attr "c86_decode" "vector") + (eq_attr "memory" "both")))) + "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ivector*3") + + (define_insn_reservation "c86_4g_m7_alu1_direct" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "alu1") + (and (eq_attr "c86_decode" "direct") + (eq_attr "memory" "none,unknown")))) + "c86-4g-m7-direct,c86-4g-m7-ieu") + + (define_insn_reservation "c86_4g_m7_alu1_direct_load" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "alu1") + (and (eq_attr "c86_decode" "direct") + (eq_attr "memory" "both")))) +@@ -320,58 +330,58 @@ (define_insn_reservation "c86_4g_m7_alu1_direct_load" 5 + + ;; CALL/CALLV + (define_insn_reservation "c86_4g_m7_call" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (eq_attr "type" "call,callv")) + "c86-4g-m7-double,c86-4g-m7-store,c86-4g-m7-bru0") + + ;; IBR + (define_insn_reservation "c86_4g_m7_branch" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ibr") + (eq_attr "memory" "none"))) + "c86-4g-m7-direct,c86-4g-m7-bru0") + + (define_insn_reservation "c86_4g_m7_branch_load" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ibr") + (eq_attr "memory" "load"))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-bru0") + + ;; LEA + (define_insn_reservation "c86_4g_m7_lea" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (eq_attr "type" "lea")) + "c86-4g-m7-direct,c86-4g-m7-ieu") + + ;; LEAVE + (define_insn_reservation "c86_4g_m7_leave" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (eq_attr "type" "leave")) + "c86-4g-m7-double,c86-4g-m7-ieu,c86-4g-m7-store") + + ;; STR + (define_insn_reservation "c86_4g_m7_str" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "str") + (eq_attr "memory" "none"))) + "c86-4g-m7-vector,c86-4g-m7-ivector*3") + + (define_insn_reservation "c86_4g_m7_str_load" 7 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "str") + (eq_attr "memory" "load"))) + "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-ivector*3") + + + (define_insn_reservation "c86_4g_m7_ieu_vector" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "other,multi") + (and (eq_attr "unit" "!i387") + (eq_attr "memory" "none,unknown")))) + "c86-4g-m7-vector,c86-4g-m7-ivector*5") + + (define_insn_reservation "c86_4g_m7_ieu_vector_load" 9 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "other,multi") + (and (eq_attr "unit" "!i387") + (eq_attr "memory" "load")))) +@@ -379,14 +389,14 @@ (define_insn_reservation "c86_4g_m7_ieu_vector_load" 9 + + ;; SSEINS + (define_insn_reservation "c86_4g_m7_sse_insertimm" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseins") + (and (eq_attr "memory" "none") + (eq_attr "length_immediate" "2")))) + "c86-4g-m7-double,c86-4g-m7-fpu_0_3,c86-4g-m7-fpu1") + + (define_insn_reservation "c86_4g_m7_sse_insert" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseins") + (and (eq_attr "memory" "none") + (eq_attr "length_immediate" "!2")))) +@@ -394,13 +404,13 @@ (define_insn_reservation "c86_4g_m7_sse_insert" 3 + + ;; FCMOV + (define_insn_reservation "c86_4g_m7_fp_cmov" 4 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (eq_attr "type" "fcmov")) + "c86-4g-m7-vector,c86-4g-m7-fvector*3") + + ;; FLD + (define_insn_reservation "c86_4g_m7_fp_mov_direct_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "c86_decode" "direct") + (and (eq_attr "type" "fmov") + (eq_attr "memory" "load")))) +@@ -408,7 +418,7 @@ (define_insn_reservation "c86_4g_m7_fp_mov_direct_load" 8 + + ;; FST + (define_insn_reservation "c86_4g_m7_fp_mov_direct_store" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "c86_decode" "direct") + (and (eq_attr "type" "fmov") + (eq_attr "memory" "store")))) +@@ -416,7 +426,7 @@ (define_insn_reservation "c86_4g_m7_fp_mov_direct_store" 8 + + ;; FILD + (define_insn_reservation "c86_4g_m7_fp_mov_double_load" 11 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "c86_decode" "double") + (and (eq_attr "type" "fmov") + (eq_attr "memory" "load")))) +@@ -424,14 +434,14 @@ (define_insn_reservation "c86_4g_m7_fp_mov_double_load" 11 + + ;; FIST + (define_insn_reservation "c86_4g_m7_fp_mov_double_store" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "c86_decode" "double") + (and (eq_attr "type" "fmov") + (eq_attr "memory" "store")))) + "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-store") + + (define_insn_reservation "c86_4g_m7_fp_mov_direct" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "c86_decode" "direct") + (and (eq_attr "type" "fmov") + (eq_attr "memory" "none")))) +@@ -439,14 +449,14 @@ (define_insn_reservation "c86_4g_m7_fp_mov_direct" 1 + + ;; FSQRT + (define_insn_reservation "c86_4g_m7_fp_sqrt" 22 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "fpspc") + (eq_attr "c86_attr" "sqrt"))) + "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x18") + + ;; FPSPC + (define_insn_reservation "c86_4g_m7_fp_spc_direct" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "fpspc") + (and (eq_attr "c86_decode" "direct") + (and (eq_attr "c86_attr" "other") +@@ -454,27 +464,27 @@ (define_insn_reservation "c86_4g_m7_fp_spc_direct" 5 + "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu3") + + (define_insn_reservation "c86_4g_m7_fp_spc" 6 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "fpspc") + (and (eq_attr "c86_attr" "other") + (eq_attr "memory" "none")))) + "c86-4g-m7-vector,c86-4g-m7-fvector*6") + + (define_insn_reservation "c86_4g_m7_fp_op_mul" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "fop,fmul") + (eq_attr "memory" "none"))) + "c86-4g-m7-direct,c86-4g-m7-fpu_0_2") + + (define_insn_reservation "c86_4g_m7_fp_op_mul_load" 12 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "fop,fmul") + (and (eq_attr "fp_int_src" "false") + (eq_attr "memory" "load")))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2") + + (define_insn_reservation "c86_4g_m7_fp_op_imul_load" 16 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "fmul") + (and (eq_attr "fp_int_src" "true") + (eq_attr "memory" "!none")))) +@@ -482,98 +492,98 @@ (define_insn_reservation "c86_4g_m7_fp_op_imul_load" 16 + + ;; FDIV + (define_insn_reservation "c86_4g_m7_fp_div" 15 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "fdiv") + (eq_attr "memory" "none"))) + "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x11") + + (define_insn_reservation "c86_4g_m7_fp_div_load" 22 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "fdiv") + (and (eq_attr "fp_int_src" "false") + (eq_attr "memory" "!none")))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x11") + + (define_insn_reservation "c86_4g_m7_fp_idiv_load" 26 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "fdiv") + (and (eq_attr "fp_int_src" "true") + (eq_attr "memory" "!none")))) + "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1*4,c86-4g-m7-fp1div1_fp3div3_x4x11") + + (define_insn_reservation "c86_4g_m7_fp_fsgn" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (eq_attr "type" "fsgn")) + "c86-4g-m7-direct,c86-4g-m7-fpu_1_3") + + ;; FCMP + (define_insn_reservation "c86_4g_m7_fp_fcmp" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "fcmp") + (eq_attr "memory" "none"))) + "c86-4g-m7-double,c86-4g-m7-fpu0,c86-4g-m7-fpu1") + + (define_insn_reservation "c86_4g_m7_fp_fcmp_load" 12 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "fcmp") + (eq_attr "memory" "load"))) + "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu0,c86-4g-m7-fpu1") + + ;; MMX + (define_insn_reservation "c86_4g_m7_fp_mmx" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (eq_attr "type" "mmx")) + "c86-4g-m7-direct") + + (define_insn_reservation "c86_4g_m7_mmx_add_cmp" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "mmxadd,mmxcmp") + (eq_attr "memory" "none"))) + "c86-4g-m7-direct,c86-4g-m7-fpu") + + (define_insn_reservation "c86_4g_m7_mmx_add_cmp_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "mmxadd,mmxcmp") + (eq_attr "memory" "load"))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu") + + (define_insn_reservation "c86_4g_m7_mmx_cvt" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "mmxcvt") + (and (eq_attr "c86_attr" "other") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-fpu_0_1") + + (define_insn_reservation "c86_4g_m7_mmx_cvt_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "mmxcvt") + (and (eq_attr "c86_attr" "other") + (eq_attr "memory" "load")))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1") + + (define_insn_reservation "c86_4g_m7_mmx_shift" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "mmxshft") + (and (eq_attr "c86_attr" "other") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-fpu1") + + (define_insn_reservation "c86_4g_m7_mmx_shift_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "mmxshft") + (and (eq_attr "c86_attr" "other") + (eq_attr "memory" "load")))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1") + + (define_insn_reservation "c86_4g_m7_mmx_shift_avg" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "mmxshft") + (and (eq_attr "c86_attr" "avg") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-fpu") + + (define_insn_reservation "c86_4g_m7_mmx_shift_avg_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "mmxshft") + (and (eq_attr "c86_attr" "avg") + (eq_attr "memory" "load")))) +@@ -581,53 +591,53 @@ (define_insn_reservation "c86_4g_m7_mmx_shift_avg_load" 8 + + ;; SADBW + (define_insn_reservation "c86_4g_m7_mmx_shift_sadbw" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "mmxshft") + (and (eq_attr "c86_attr" "sadbw") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-fpu0") + + (define_insn_reservation "c86_4g_m7_mmx_shift_sadbw_load" 10 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "mmxshft") + (and (eq_attr "c86_attr" "sadbw") + (eq_attr "memory" "load")))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0") + + (define_insn_reservation "c86_4g_m7_mmx_mov" 4 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "mmxmov") + (eq_attr "memory" "none"))) + "c86-4g-m7-direct,c86-4g-m7-fpu1") + + (define_insn_reservation "c86_4g_m7_mmx_mov_store" 4 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "mmxmov") + (and (eq_attr "c86_attr" "other") + (eq_attr "memory" "store")))) + "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1") + + (define_insn_reservation "c86_4g_m7_mmx_mov_load" 11 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "mmxmov") + (eq_attr "memory" "load"))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1") + + (define_insn_reservation "c86_4g_m7_mmx_mul" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "mmxmul") + (eq_attr "memory" "none"))) + "c86-4g-m7-direct,c86-4g-m7-fpu0") + + (define_insn_reservation "c86_4g_m7_mmx_mul_load" 10 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "mmxmul") + (eq_attr "memory" "load"))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0") + + ;; PINSR + (define_insn_reservation "c86_4g_m7_sse_pinsr_reg" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog,mmxcvt") + (and (eq_attr "c86_attr" "insr") + (and (eq_attr "prefix" "orig") +@@ -635,7 +645,7 @@ (define_insn_reservation "c86_4g_m7_sse_pinsr_reg" 1 + "c86-4g-m7-direct,c86-4g-m7-fpu") + + (define_insn_reservation "c86_4g_m7_sse_pinsr_reg_load" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog,mmxcvt") + (and (eq_attr "c86_attr" "insr") + (and (eq_attr "prefix" "orig") +@@ -643,7 +653,7 @@ (define_insn_reservation "c86_4g_m7_sse_pinsr_reg_load" 3 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu") + + (define_insn_reservation "c86_4g_m7_avx_vpinsr_reg" 2 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (eq_attr "c86_attr" "insr") + (and (eq_attr "prefix" "!orig") +@@ -651,7 +661,7 @@ (define_insn_reservation "c86_4g_m7_avx_vpinsr_reg" 2 + "c86-4g-m7-double,c86-4g-m7-fpu_1_3x2") + + (define_insn_reservation "c86_4g_m7_avx_vpinsr_reg_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (eq_attr "c86_attr" "insr") + (and (eq_attr "prefix" "!orig") +@@ -660,7 +670,7 @@ (define_insn_reservation "c86_4g_m7_avx_vpinsr_reg_load" 8 + + ;; PERM + (define_insn_reservation "c86_4g_m7_avx512_perm_xmm" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (ior (and (eq_attr "c86_attr" "perm2") + (eq_attr "mode" "V4SF,V2DF,TI")) +@@ -670,7 +680,7 @@ (define_insn_reservation "c86_4g_m7_avx512_perm_xmm" 3 + "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2") + + (define_insn_reservation "c86_4g_m7_avx512_perm_xmm_opload" 10 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (ior (and (eq_attr "c86_attr" "perm2") + (eq_attr "mode" "V4SF,V2DF,TI")) +@@ -680,7 +690,7 @@ (define_insn_reservation "c86_4g_m7_avx512_perm_xmm_opload" 10 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2") + + (define_insn_reservation "c86_4g_m7_avx512_permi2_ymm" 4 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (eq_attr "c86_attr" "perm2") + (and (eq_attr "mode" "V8SF,V4DF,OI") +@@ -688,7 +698,7 @@ (define_insn_reservation "c86_4g_m7_avx512_permi2_ymm" 4 + "c86-4g-m7-vector,c86-4g-m7-fpux4") + + (define_insn_reservation "c86_4g_m7_avx512_permi2_zmm" 16 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (eq_attr "c86_attr" "perm2") + (and (eq_attr "mode" "V16SF,V8DF,XI") +@@ -696,7 +706,7 @@ (define_insn_reservation "c86_4g_m7_avx512_permi2_zmm" 16 + "c86-4g-m7-vector,c86-4g-m7-fpux16") + + (define_insn_reservation "c86_4g_m7_avx512_permi2_ymm_load" 11 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (eq_attr "c86_attr" "perm2") + (and (eq_attr "mode" "V8SF,V4DF,OI") +@@ -704,7 +714,7 @@ (define_insn_reservation "c86_4g_m7_avx512_permi2_ymm_load" 11 + "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux4") + + (define_insn_reservation "c86_4g_m7_avx512_permi2_zmm_load" 23 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (eq_attr "c86_attr" "perm2") + (and (eq_attr "mode" "V16SF,V8DF,XI") +@@ -712,7 +722,7 @@ (define_insn_reservation "c86_4g_m7_avx512_permi2_zmm_load" 23 + "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux16") + + (define_insn_reservation "c86_4g_m7_avx512_perm_zmm_imm" 4 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (eq_attr "c86_attr" "perm") + (and (eq_attr "mode" "V16SF,V8DF,XI") +@@ -721,7 +731,7 @@ (define_insn_reservation "c86_4g_m7_avx512_perm_zmm_imm" 4 + "c86-4g-m7-direct,c86-4g-m7-fpux4") + + (define_insn_reservation "c86_4g_m7_avx512_perm_zmm_imm_load" 11 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (eq_attr "c86_attr" "perm") + (and (eq_attr "mode" "V16SF,V8DF,XI") +@@ -730,7 +740,7 @@ (define_insn_reservation "c86_4g_m7_avx512_perm_zmm_imm_load" 11 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpux4") + + (define_insn_reservation "c86_4g_m7_avx512_perm_zmm_noimm" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (eq_attr "c86_attr" "perm") + (and (eq_attr "mode" "V16SF,V8DF,XI") +@@ -739,7 +749,7 @@ (define_insn_reservation "c86_4g_m7_avx512_perm_zmm_noimm" 8 + "c86-4g-m7-vector,c86-4g-m7-fpux8") + + (define_insn_reservation "c86_4g_m7_sse_perm_zmm_noimm_load" 15 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (eq_attr "c86_attr" "perm") + (and (eq_attr "mode" "V16SF,V8DF,XI") +@@ -749,7 +759,7 @@ (define_insn_reservation "c86_4g_m7_sse_perm_zmm_noimm_load" 15 + + ;; VINSERT + (define_insn_reservation "c86_4g_m7_avx512_insertx_ymm" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog,sselog1") + (and (eq_attr "c86_attr" "insertx") + (and (eq_attr "mode" "V8SF,V4DF,OI") +@@ -758,7 +768,7 @@ (define_insn_reservation "c86_4g_m7_avx512_insertx_ymm" 3 + "c86-4g-m7-direct,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_0_2") + + (define_insn_reservation "c86_4g_m7_avx512_insertx_ymem" 10 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog,sselog1") + (and (eq_attr "c86_attr" "insertx") + (and (eq_attr "mode" "V8SF,V4DF,OI") +@@ -767,7 +777,7 @@ (define_insn_reservation "c86_4g_m7_avx512_insertx_ymem" 10 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_0_2") + + (define_insn_reservation "c86_4g_m7_avx512_insertx_zxmm" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (eq_attr "c86_attr" "insertx") + (and (eq_attr "mode" "V16SF,V8DF,XI") +@@ -776,7 +786,7 @@ (define_insn_reservation "c86_4g_m7_avx512_insertx_zxmm" 5 + "c86-4g-m7-double,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2") + + (define_insn_reservation "c86_4g_m7_avx512_insertx_zxmem" 12 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (eq_attr "c86_attr" "insertx") + (and (eq_attr "mode" "V16SF,V8DF,XI") +@@ -785,7 +795,7 @@ (define_insn_reservation "c86_4g_m7_avx512_insertx_zxmem" 12 + "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2") + + (define_insn_reservation "c86_4g_m7_avx512_insertx_zymm" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (eq_attr "c86_attr" "insertx") + (and (eq_attr "mode" "V16SF,V8DF,XI") +@@ -794,7 +804,7 @@ (define_insn_reservation "c86_4g_m7_avx512_insertx_zymm" 1 + "c86-4g-m7-double,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_insertx_zymem" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (eq_attr "c86_attr" "insertx") + (and (eq_attr "mode" "V16SF,V8DF,XI") +@@ -803,7 +813,7 @@ (define_insn_reservation "c86_4g_m7_avx512_insertx_zymem" 8 + "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx_insertx_ymm" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog,sselog1") + (and (eq_attr "c86_attr" "insertx") + (and (eq_attr "prefix" "!evex") +@@ -811,7 +821,7 @@ (define_insn_reservation "c86_4g_m7_avx_insertx_ymm" 3 + "c86-4g-m7-direct,c86-4g-m7-fpu0*2") + + (define_insn_reservation "c86_4g_m7_avx_insertx_ymem" 10 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog,sselog1") + (and (eq_attr "c86_attr" "insertx") + (and (eq_attr "prefix" "!evex") +@@ -820,7 +830,7 @@ (define_insn_reservation "c86_4g_m7_avx_insertx_ymem" 10 + + ;; SHUF/MULTISHIFTQB + (define_insn_reservation "c86_4g_m7_avx512_shuf_xymm" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (eq_attr "c86_attr" "shufx") + (and (not (eq_attr "mode" "V8DF,V16SF,XI")) +@@ -828,7 +838,7 @@ (define_insn_reservation "c86_4g_m7_avx512_shuf_xymm" 3 + "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2") + + (define_insn_reservation "c86_4g_m7_avx512_shuf_zmm" 4 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (eq_attr "c86_attr" "shufx") + (and (eq_attr "mode" "V8DF,V16SF,XI") +@@ -836,7 +846,7 @@ (define_insn_reservation "c86_4g_m7_avx512_shuf_zmm" 4 + "c86-4g-m7-vector,c86-4g-m7-fpu_0_2x4") + + (define_insn_reservation "c86_4g_m7_avx512_shuf_xymem" 10 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (eq_attr "c86_attr" "shufx") + (and (not (eq_attr "mode" "V8DF,V16SF,XI")) +@@ -844,7 +854,7 @@ (define_insn_reservation "c86_4g_m7_avx512_shuf_xymem" 10 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2") + + (define_insn_reservation "c86_4g_m7_avx512_shuf_zmem" 11 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (eq_attr "c86_attr" "shufx") + (and (eq_attr "mode" "V8DF,V16SF,XI") +@@ -853,14 +863,14 @@ (define_insn_reservation "c86_4g_m7_avx512_shuf_zmem" 11 + + ;; SSELOGIC + (define_insn_reservation "c86_4g_m7_sselogic_xymm" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog,sselog1") + (and (eq_attr "c86_attr" "sselogic") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-fpu") + + (define_insn_reservation "c86_4g_m7_sselogic_xymm_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog,sselog1") + (and (eq_attr "c86_attr" "sselogic") + (eq_attr "memory" "load")))) +@@ -868,14 +878,14 @@ (define_insn_reservation "c86_4g_m7_sselogic_xymm_load" 8 + + ;; CMPESTR + (define_insn_reservation "c86_4g_m7_avx512_cmpestr" 6 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (eq_attr "c86_attr" "cmpestr") + (eq_attr "memory" "none")))) + "c86-4g-m7-vector,c86-4g-m7-fpux6") + + (define_insn_reservation "c86_4g_m7_avx512_cmpestr_load" 13 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog") + (and (eq_attr "c86_attr" "cmpestr") + (eq_attr "memory" "load")))) +@@ -883,14 +893,14 @@ (define_insn_reservation "c86_4g_m7_avx512_cmpestr_load" 13 + + ;; SSELOG + (define_insn_reservation "c86_4g_m7_avx512_log" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1") + (and (eq_attr "c86_attr" "other") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_log_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1") + (and (eq_attr "c86_attr" "other") + (eq_attr "memory" "load")))) +@@ -899,7 +909,7 @@ (define_insn_reservation "c86_4g_m7_avx512_log_load" 8 + ;; SSELOG1 + ;; VDBPSADBW + (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_xymm" 4 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog1") + (and (eq_attr "c86_attr" "sadbw") + (and (eq_attr "mode" "OI,TI") +@@ -907,7 +917,7 @@ (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_xymm" 4 + "c86-4g-m7-double,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_xymem" 11 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog1") + (and (eq_attr "c86_attr" "sadbw") + (and (eq_attr "mode" "OI,TI") +@@ -915,7 +925,7 @@ (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_xymem" 11 + "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_zmm" 4 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog1") + (and (eq_attr "c86_attr" "sadbw") + (and (eq_attr "mode" "XI") +@@ -923,7 +933,7 @@ (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_zmm" 4 + "c86-4g-m7-vector,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3x2") + + (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_zmem" 11 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog1") + (and (eq_attr "c86_attr" "sadbw") + (and (eq_attr "mode" "XI") +@@ -932,7 +942,7 @@ (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_zmem" 11 + + ;; ABS + (define_insn_reservation "c86_4g_m7_avx512_abs" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog1,sse") + (and (eq_attr "c86_attr" "abs") + (and (eq_attr "prefix" "evex") +@@ -940,7 +950,7 @@ (define_insn_reservation "c86_4g_m7_avx512_abs" 1 + "c86-4g-m7-direct,c86-4g-m7-fpu") + + (define_insn_reservation "c86_4g_m7_avx512_abs_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog1,sse") + (and (eq_attr "c86_attr" "abs") + (and (eq_attr "prefix" "evex") +@@ -949,14 +959,14 @@ (define_insn_reservation "c86_4g_m7_avx512_abs_load" 8 + + ;; SIGN + (define_insn_reservation "c86_4g_m7_avx_sign" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog1") + (and (eq_attr "c86_attr" "sign") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-fpu_0_3") + + (define_insn_reservation "c86_4g_m7_avx_sign_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog1") + (and (eq_attr "c86_attr" "sign") + (eq_attr "memory" "!none")))) +@@ -964,7 +974,7 @@ (define_insn_reservation "c86_4g_m7_avx_sign_load" 8 + + ;; BLEND/ABS/AES + (define_insn_reservation "c86_4g_m7_avx_blend" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog1") + (and (eq_attr "c86_attr" "abs,blend,aes") + (and (eq_attr "prefix" "!evex") +@@ -972,7 +982,7 @@ (define_insn_reservation "c86_4g_m7_avx_blend" 1 + "c86-4g-m7-direct,c86-4g-m7-fpu_0_1") + + (define_insn_reservation "c86_4g_m7_avx_blend_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog1") + (and (eq_attr "c86_attr" "abs,blend,aes") + (and (eq_attr "prefix" "!evex") +@@ -980,7 +990,7 @@ (define_insn_reservation "c86_4g_m7_avx_blend_load" 8 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1") + + (define_insn_reservation "c86_4g_m7_avx512_aes" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog1,ssecvt,sse") + (and (eq_attr "c86_attr" "aes") + (and (eq_attr "prefix" "evex") +@@ -988,7 +998,7 @@ (define_insn_reservation "c86_4g_m7_avx512_aes" 3 + "c86-4g-m7-direct,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_aes_load" 10 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog1,ssecvt,sse") + (and (eq_attr "c86_attr" "aes") + (and (eq_attr "prefix" "evex") +@@ -996,7 +1006,7 @@ (define_insn_reservation "c86_4g_m7_avx512_aes_load" 10 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx_aes" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog1") + (and (eq_attr "c86_attr" "aes") + (and (eq_attr "prefix" "!evex") +@@ -1004,7 +1014,7 @@ (define_insn_reservation "c86_4g_m7_avx_aes" 3 + "c86-4g-m7-direct,c86-4g-m7-fpu_0_1") + + (define_insn_reservation "c86_4g_m7_avx_aes_load" 10 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog1") + (and (eq_attr "c86_attr" "aes") + (and (eq_attr "prefix" "!evex") +@@ -1013,14 +1023,14 @@ (define_insn_reservation "c86_4g_m7_avx_aes_load" 10 + + ;; EXTR + (define_insn_reservation "c86_4g_m7_extr" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog1,sselog,mmxcvt") + (and (eq_attr "c86_attr" "extr") + (eq_attr "memory" "none")))) + "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1") + + (define_insn_reservation "c86_4g_m7_extr_store" 12 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sselog1,sselog,mmxcvt") + (and (eq_attr "c86_attr" "extr") + (eq_attr "memory" "store")))) +@@ -1028,28 +1038,28 @@ (define_insn_reservation "c86_4g_m7_extr_store" 12 + + ;; SSECOMI + (define_insn_reservation "c86_4g_m7_avx_ssecomi_comi" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecomi") + (and (eq_attr "prefix_extra" "0") + (eq_attr "memory" "none")))) + "c86-4g-m7-double,c86-4g-m7-fpu") + + (define_insn_reservation "c86_4g_m7_avx_ssecomi_comi_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecomi") + (and (eq_attr "prefix_extra" "0") + (eq_attr "memory" "load")))) + "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu") + + (define_insn_reservation "c86_4g_m7_avx_ssecomi_test" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecomi") + (and (eq_attr "prefix_extra" "1") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-fpu1|c86-4g-m7-fpu2") + + (define_insn_reservation "c86_4g_m7_avx_ssecomi_test_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecomi") + (and (eq_attr "prefix_extra" "1") + (eq_attr "memory" "load")))) +@@ -1057,28 +1067,28 @@ (define_insn_reservation "c86_4g_m7_avx_ssecomi_test_load" 8 + + ;; SSEIMUL + (define_insn_reservation "c86_4g_m7_avx512_imul" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseimul") + (and (eq_attr "prefix" "evex") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-fpu_0_2") + + (define_insn_reservation "c86_4g_m7_avx512_imul_mem" 10 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseimul") + (and (eq_attr "prefix" "evex") + (eq_attr "memory" "load")))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2") + + (define_insn_reservation "c86_4g_m7_avx_imul" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseimul") + (and (eq_attr "prefix" "!evex") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-fpu_0_3") + + (define_insn_reservation "c86_4g_m7_avx_imul_mem" 10 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseimul") + (and (eq_attr "prefix" "!evex") + (eq_attr "memory" "load")))) +@@ -1086,28 +1096,28 @@ (define_insn_reservation "c86_4g_m7_avx_imul_mem" 10 + + ;; SSEMOV + (define_insn_reservation "c86_4g_m7_avx512_mov_vmov" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemov,sseiadd") + (and (eq_attr "c86_attr" "other,blend,maxmin") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-fpu") + + (define_insn_reservation "c86_4g_m7_avx512_mov_vmov_store" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemov") + (and (eq_attr "c86_attr" "other") +- (eq_attr "memory" "store")))) ++ (eq_attr "memory" "store")))) + "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1") + + (define_insn_reservation "c86_4g_m7_avx512_mov_vmov_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemov,sseiadd") + (and (eq_attr "c86_attr" "other,blend,maxmin") + (eq_attr "memory" "load")))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu") + + (define_insn_reservation "c86_4g_m7_avx512_vpmovx_y" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemov") + (and (eq_attr "c86_attr" "vpmovx") + (and (eq_attr "prefix" "evex") +@@ -1116,7 +1126,7 @@ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_y" 3 + "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2") + + (define_insn_reservation "c86_4g_m7_avx512_vpmovx_y_load" 10 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemov,sselog1") + (and (eq_attr "c86_attr" "vpmovx") + (and (eq_attr "prefix" "evex") +@@ -1125,7 +1135,7 @@ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_y_load" 10 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-fpu_0_2x2") + + (define_insn_reservation "c86_4g_m7_avx512_vpmovx_z" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemov") + (and (eq_attr "c86_attr" "vpmovx") + (and (eq_attr "mode" "XI") +@@ -1133,7 +1143,7 @@ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_z" 5 + "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x4") + + (define_insn_reservation "c86_4g_m7_avx512_vpmovx_z_load" 12 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemov") + (and (eq_attr "c86_attr" "vpmovx") + (and (eq_attr "mode" "XI") +@@ -1141,7 +1151,7 @@ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_z_load" 12 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4") + + (define_insn_reservation "c86_4g_m7_avx512_vpmovx_x" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemov") + (and (eq_attr "c86_attr" "vpmovx") + (and (eq_attr "prefix" "evex") +@@ -1150,7 +1160,7 @@ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_x" 1 + "c86-4g-m7-direct,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_vpmovx_x_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemov") + (and (eq_attr "c86_attr" "vpmovx") + (and (eq_attr "prefix" "evex") +@@ -1159,7 +1169,7 @@ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_x_load" 8 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx_vpmovx_xx" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemov") + (and (eq_attr "c86_attr" "vpmovx") + (and (eq_attr "prefix" "!evex") +@@ -1167,7 +1177,7 @@ (define_insn_reservation "c86_4g_m7_avx_vpmovx_xx" 1 + "c86-4g-m7-direct,c86-4g-m7-fpu1|c86-4g-m7-fpu2") + + (define_insn_reservation "c86_4g_m7_avx_vpmovx_xx_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemov") + (and (eq_attr "c86_attr" "vpmovx") + (and (eq_attr "prefix" "!evex") +@@ -1176,7 +1186,7 @@ (define_insn_reservation "c86_4g_m7_avx_vpmovx_xx_load" 8 + + ;; EXPAND + (define_insn_reservation "c86_4g_m7_avx512_expand" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemov") + (and (eq_attr "c86_attr" "expand,compress") + (and (not (eq_attr "mode" "XI,V16SF,V8DF")) +@@ -1184,7 +1194,7 @@ (define_insn_reservation "c86_4g_m7_avx512_expand" 3 + "c86-4g-m7-direct,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3") + + (define_insn_reservation "c86_4g_m7_avx512_expand_load" 10 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemov") + (and (eq_attr "c86_attr" "expand,compress") + (and (not (eq_attr "mode" "XI,V16SF,V8DF")) +@@ -1192,7 +1202,7 @@ (define_insn_reservation "c86_4g_m7_avx512_expand_load" 10 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3") + + (define_insn_reservation "c86_4g_m7_avx512_expand_z" 10 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemov") + (and (eq_attr "c86_attr" "expand,compress") + (and (eq_attr "mode" "XI,V16SF,V8DF") +@@ -1200,7 +1210,7 @@ (define_insn_reservation "c86_4g_m7_avx512_expand_z" 10 + "c86-4g-m7-vector,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3") + + (define_insn_reservation "c86_4g_m7_avx512_expand_z_load" 17 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemov") + (and (eq_attr "c86_attr" "expand,compress") + (and (eq_attr "mode" "XI,V16SF,V8DF") +@@ -1209,7 +1219,7 @@ (define_insn_reservation "c86_4g_m7_avx512_expand_z_load" 17 + + ;; MOVNT + (define_insn_reservation "c86_4g_m7_avx512_movnt_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemov") + (and (eq_attr "c86_attr" "movnt") + (and (eq_attr "mode" "XI,V16SF,V8DF") +@@ -1217,7 +1227,7 @@ (define_insn_reservation "c86_4g_m7_avx512_movnt_load" 8 + "c86-4g-m7-double,c86-4g-m7-load") + + (define_insn_reservation "c86_4g_m7_avx512_movnt_store" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemov") + (and (eq_attr "c86_attr" "movnt") + (and (eq_attr "mode" "XI,V16SF,V8DF") +@@ -1225,7 +1235,7 @@ (define_insn_reservation "c86_4g_m7_avx512_movnt_store" 8 + "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1*2") + + (define_insn_reservation "c86_4g_m7_sse_movnt_store" 4 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemov,mmxmov") + (and (eq_attr "c86_attr" "movnt") + (and (not (eq_attr "mode" "XI,V16SF,V8DF")) +@@ -1233,7 +1243,7 @@ (define_insn_reservation "c86_4g_m7_sse_movnt_store" 4 + "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1") + + (define_insn_reservation "c86_4g_m7_sse_movnt" 4 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemov") + (and (eq_attr "c86_attr" "movnt") + (and (not (eq_attr "mode" "XI,V16SF,V8DF")) +@@ -1242,14 +1252,14 @@ (define_insn_reservation "c86_4g_m7_sse_movnt" 4 + + ;; BLENDV + (define_insn_reservation "c86_4g_m7_avx512_blendv" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemov") + (and (eq_attr "c86_attr" "blendv") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-fpu_0_1") + + (define_insn_reservation "c86_4g_m7_avx512_blendv_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemov") + (and (eq_attr "c86_attr" "blendv") + (eq_attr "memory" "load")))) +@@ -1257,7 +1267,7 @@ (define_insn_reservation "c86_4g_m7_avx512_blendv_load" 8 + + ;; SSEISHFT + (define_insn_reservation "c86_4g_m7_avx512_sseishft_aligr" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseishft") + (and (eq_attr "prefix_extra" "1") + (and (eq_attr "prefix" "evex") +@@ -1265,7 +1275,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sseishft_aligr" 1 + "c86-4g-m7-direct,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_sseishft_aligr_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseishft") + (and (eq_attr "prefix_extra" "1") + (and (eq_attr "prefix" "evex") +@@ -1273,14 +1283,14 @@ (define_insn_reservation "c86_4g_m7_avx512_sseishft_aligr_load" 8 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_sseishft_vshift" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseishft") + (and (eq_attr "prefix_extra" "!1") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-fpu_0_2") + + (define_insn_reservation "c86_4g_m7_avx512_sseishft_vshift_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseishft") + (and (eq_attr "prefix_extra" "!1") + (eq_attr "memory" "!none")))) +@@ -1289,23 +1299,23 @@ (define_insn_reservation "c86_4g_m7_avx512_sseishft_vshift_load" 8 + + ;; SSEADD + (define_insn_reservation "c86_4g_m7_avx512_sseadd_maxmin" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseadd,sse") + (and (eq_attr "c86_attr" "maxmin") + (and (eq_attr "prefix" "evex") +- (eq_attr "memory" "none"))))) ++ (eq_attr "memory" "none"))))) + "c86-4g-m7-direct,c86-4g-m7-fpu_0_2") + + (define_insn_reservation "c86_4g_m7_avx512_sseadd_maxmin_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseadd,sse") + (and (eq_attr "c86_attr" "maxmin") + (and (eq_attr "prefix" "evex") +- (eq_attr "memory" "load"))))) ++ (eq_attr "memory" "load"))))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2") + + (define_insn_reservation "c86_4g_m7_avx_sseadd_maxmin" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseadd,sse") + (and (eq_attr "c86_attr" "maxmin") + (and (eq_attr "prefix" "vex") +@@ -1313,7 +1323,7 @@ (define_insn_reservation "c86_4g_m7_avx_sseadd_maxmin" 1 + "c86-4g-m7-direct,c86-4g-m7-fpu_0_1") + + (define_insn_reservation "c86_4g_m7_avx_sseadd_maxmin_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseadd,sse") + (and (eq_attr "c86_attr" "maxmin") + (and (eq_attr "prefix" "vex") +@@ -1321,7 +1331,7 @@ (define_insn_reservation "c86_4g_m7_avx_sseadd_maxmin_load" 8 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1") + + (define_insn_reservation "c86_4g_m7_sse_sseadd_maxmin" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseadd,sse") + (and (eq_attr "c86_attr" "maxmin") + (and (eq_attr "prefix" "orig") +@@ -1329,7 +1339,7 @@ (define_insn_reservation "c86_4g_m7_sse_sseadd_maxmin" 1 + "c86-4g-m7-direct,c86-4g-m7-fpu2|c86-4g-m7-fpu3") + + (define_insn_reservation "c86_4g_m7_sse_sseadd_maxmin_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseadd,sse") + (and (eq_attr "c86_attr" "maxmin") + (and (eq_attr "prefix" "orig") +@@ -1338,29 +1348,29 @@ (define_insn_reservation "c86_4g_m7_sse_sseadd_maxmin_load" 8 + + ;; SUB/ADD + (define_insn_reservation "c86_4g_m7_avx512_sseadd" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseadd") + (and (eq_attr "c86_attr" "other") +- (eq_attr "memory" "none")))) ++ (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_sseadd_load" 10 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseadd") + (and (eq_attr "c86_attr" "other") +- (eq_attr "memory" "load")))) ++ (eq_attr "memory" "load")))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3") + + ;; HADD/HSUB + (define_insn_reservation "c86_4g_m7_avx_sseadd_hplus" 7 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseadd,sseadd1") + (and (eq_attr "c86_attr" "hplus") + (eq_attr "memory" "none")))) + "c86-4g-m7-vector") + + (define_insn_reservation "c86_4g_m7_avx_sseadd_hplus_load" 14 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseadd,sseadd1") + (and (eq_attr "c86_attr" "hplus") + (eq_attr "memory" "load")))) +@@ -1368,7 +1378,7 @@ (define_insn_reservation "c86_4g_m7_avx_sseadd_hplus_load" 14 + + ;; SSEIADD + (define_insn_reservation "c86_4g_m7_avx512_sseiadd_madd" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseiadd") + (and (eq_attr "c86_attr" "sadbw,madd") + (and (ior (eq_attr "prefix" "evex") +@@ -1377,7 +1387,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sseiadd_madd" 3 + "c86-4g-m7-direct,c86-4g-m7-fpu_0_2") + + (define_insn_reservation "c86_4g_m7_avx512_sseiadd_madd_mem" 10 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseiadd") + (and (eq_attr "c86_attr" "sadbw,madd") + (and (ior (eq_attr "prefix" "evex") +@@ -1386,7 +1396,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sseiadd_madd_mem" 10 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2") + + (define_insn_reservation "c86_4g_m7_avx_sseiadd_sadbw" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseiadd") + (and (eq_attr "c86_attr" "sadbw") + (and (eq_attr "prefix" "vex,maybe_evex") +@@ -1395,7 +1405,7 @@ (define_insn_reservation "c86_4g_m7_avx_sseiadd_sadbw" 3 + "c86-4g-m7-direct,c86-4g-m7-fpu_0_1") + + (define_insn_reservation "c86_4g_m7_avx_sseiadd_sadbw_mem" 10 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseiadd") + (and (eq_attr "c86_attr" "sadbw") + (and (eq_attr "prefix" "vex,maybe_evex") +@@ -1404,7 +1414,7 @@ (define_insn_reservation "c86_4g_m7_avx_sseiadd_sadbw_mem" 10 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1") + + (define_insn_reservation "c86_4g_m7_sse_sseiadd_sadbw" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseiadd") + (and (eq_attr "c86_attr" "sadbw") + (and (eq_attr "prefix" "orig") +@@ -1412,7 +1422,7 @@ (define_insn_reservation "c86_4g_m7_sse_sseiadd_sadbw" 3 + "c86-4g-m7-direct,c86-4g-m7-fpu_0_3") + + (define_insn_reservation "c86_4g_m7_sse_sseiadd_sadbw_mem" 10 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseiadd") + (and (eq_attr "c86_attr" "sadbw") + (and (eq_attr "prefix" "orig") +@@ -1420,7 +1430,7 @@ (define_insn_reservation "c86_4g_m7_sse_sseiadd_sadbw_mem" 10 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_3") + + (define_insn_reservation "c86_4g_m7_sse_sseiadd_madd" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseiadd") + (and (eq_attr "c86_attr" "madd") + (and (eq_attr "prefix" "!evex") +@@ -1428,7 +1438,7 @@ (define_insn_reservation "c86_4g_m7_sse_sseiadd_madd" 3 + "c86-4g-m7-direct,c86-4g-m7-fpu0") + + (define_insn_reservation "c86_4g_m7_sse_sseiadd_madd_mem" 10 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseiadd") + (and (eq_attr "c86_attr" "madd") + (and (eq_attr "prefix" "!evex") +@@ -1437,21 +1447,21 @@ (define_insn_reservation "c86_4g_m7_sse_sseiadd_madd_mem" 10 + + ;; AVG + (define_insn_reservation "c86_4g_m7_avx512_sseiadd_avg" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseiadd") + (and (eq_attr "c86_attr" "avg") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-fpu") + + (define_insn_reservation "c86_4g_m7_avx512_sseiadd_avg_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseiadd") + (and (eq_attr "c86_attr" "avg") + (eq_attr "memory" "load")))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu") + + (define_insn_reservation "c86_4g_m7_avx_sseiadd_hplus" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseiadd,sseiadd1") + (and (eq_attr "c86_attr" "hplus") + (and (eq_attr "prefix" "vex") +@@ -1459,7 +1469,7 @@ (define_insn_reservation "c86_4g_m7_avx_sseiadd_hplus" 3 + "c86-4g-m7-vector") + + (define_insn_reservation "c86_4g_m7_avx_sseiadd_hplus_load" 10 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseiadd,sseiadd1") + (and (eq_attr "c86_attr" "hplus") + (and (eq_attr "prefix" "vex") +@@ -1467,15 +1477,15 @@ (define_insn_reservation "c86_4g_m7_avx_sseiadd_hplus_load" 10 + "c86-4g-m7-vector,c86-4g-m7-load") + + (define_insn_reservation "c86_4g_m7_sse_sseiadd_hplus" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseiadd,sseiadd1") + (and (eq_attr "c86_attr" "hplus") + (and (eq_attr "prefix" "orig") +- (eq_attr "memory" "none"))))) ++ (eq_attr "memory" "none"))))) + "c86-4g-m7-vector,c86-4g-m7-fpux2") + + (define_insn_reservation "c86_4g_m7_sse_sseiadd_hplus_load" 10 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sseiadd,sseiadd1") + (and (eq_attr "c86_attr" "hplus") + (and (eq_attr "prefix" "orig") +@@ -1495,44 +1505,56 @@ (define_insn_reservation "c86_4g_m7_avx512_ssemul_load" 10 + (eq_attr "memory" "load"))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2") + ++(define_insn_reservation "c86_4g_m8_avx512_ssemul" 4 ++ (and (eq_attr "cpu" "c86_4g_m8") ++ (and (eq_attr "type" "ssemul") ++ (eq_attr "memory" "none"))) ++ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2") ++ ++(define_insn_reservation "c86_4g_m8_avx512_ssemul_load" 11 ++ (and (eq_attr "cpu" "c86_4g_m8") ++ (and (eq_attr "type" "ssemul") ++ (eq_attr "memory" "load"))) ++ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2") ++ + ;; SSEDIV + (define_insn_reservation "c86_4g_m7_avx512_ssediv_x" 13 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssediv") + (and (eq_attr "mode" "SF,DF,V4SF,V2DF") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x8") + + (define_insn_reservation "c86_4g_m7_avx512_ssediv_xmem" 20 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssediv") + (and (eq_attr "mode" "SF,DF,V4SF,V2DF") + (eq_attr "memory" "load")))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x8") + + (define_insn_reservation "c86_4g_m7_avx512_ssediv_y" 13 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssediv") + (and (eq_attr "mode" "V8SF,V4DF") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*8") + + (define_insn_reservation "c86_4g_m7_avx512_ssediv_ymem" 20 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssediv") + (and (eq_attr "mode" "V8SF,V4DF") + (eq_attr "memory" "load")))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*8") + + (define_insn_reservation "c86_4g_m7_avx512_ssediv_z" 24 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssediv") + (and (eq_attr "mode" "V16SF,V8DF") + (eq_attr "memory" "none")))) + "c86-4g-m7-double,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*20") + + (define_insn_reservation "c86_4g_m7_avx512_ssediv_zmem" 31 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssediv") + (and (eq_attr "mode" "V16SF,V8DF") + (eq_attr "memory" "load")))) +@@ -1540,7 +1562,7 @@ (define_insn_reservation "c86_4g_m7_avx512_ssediv_zmem" 31 + + ;; SSECMP + (define_insn_reservation "c86_4g_m7_avx512_ssecmp" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecmp") + (and (eq_attr "prefix" "evex") + (and (eq_attr "mode" "V2DF,V4DF,V8SF,V4SF,SF,DF") +@@ -1548,7 +1570,7 @@ (define_insn_reservation "c86_4g_m7_avx512_ssecmp" 5 + "c86-4g-m7-double,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_ssecmp_load" 12 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecmp") + (and (eq_attr "prefix" "evex") + (and (eq_attr "mode" "V2DF,V4DF,V8SF,V4SF,SF,DF") +@@ -1556,7 +1578,7 @@ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_load" 12 + "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_ssecmp_z" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecmp") + (and (eq_attr "mode" "V16SF,V8DF,XI") + (and (eq_attr "c86_attr" "other") +@@ -1564,7 +1586,7 @@ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_z" 5 + "c86-4g-m7-vector,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_ssecmp_z_load" 12 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecmp") + (and (eq_attr "mode" "V16SF,V8DF,XI") + (and (eq_attr "c86_attr" "other") +@@ -1572,7 +1594,7 @@ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_z_load" 12 + "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3x2") + + (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecmp") + (and (eq_attr "prefix" "evex") + (and (eq_attr "mode" "TI,OI") +@@ -1581,7 +1603,7 @@ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp" 5 + "c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_load" 12 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecmp") + (and (eq_attr "prefix" "evex") + (and (eq_attr "mode" "TI,OI") +@@ -1590,7 +1612,7 @@ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_load" 12 + "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_z" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecmp") + (and (eq_attr "prefix" "evex") + (and (eq_attr "mode" "XI") +@@ -1599,7 +1621,7 @@ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_z" 5 + "c86-4g-m7-vector,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_z_load" 12 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecmp") + (and (eq_attr "prefix" "evex") + (and (eq_attr "mode" "XI") +@@ -1608,14 +1630,14 @@ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_z_load" 12 + "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3x2") + + (define_insn_reservation "c86_4g_m7_avx_ssecmp_vp" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecmp") + (and (eq_attr "prefix" "!evex") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-fpu") + + (define_insn_reservation "c86_4g_m7_avx_ssecmp_vp_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecmp") + (and (eq_attr "prefix" "!evex") + (eq_attr "memory" "load")))) +@@ -1623,7 +1645,7 @@ (define_insn_reservation "c86_4g_m7_avx_ssecmp_vp_load" 8 + + ;; VPTEST + (define_insn_reservation "c86_4g_m7_avx512_ssecmp_test" 6 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecmp") + (and (eq_attr "mode" "TI,OI") + (and (eq_attr "c86_attr" "ptest") +@@ -1631,7 +1653,7 @@ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_test" 6 + "c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_ssecmp_test_load" 13 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecmp") + (and (eq_attr "mode" "TI,OI") + (and (eq_attr "c86_attr" "ptest") +@@ -1640,7 +1662,7 @@ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_test_load" 13 + + ;; SSECVT + (define_insn_reservation "c86_4g_m7_avx512_ssecvt_xy" 4 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecvt") + (and (eq_attr "c86_attr" "other") + (and (eq_attr "prefix" "evex") +@@ -1651,7 +1673,7 @@ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_xy" 4 + "c86-4g-m7-direct,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_ssecvt_xy_load" 11 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecvt") + (and (eq_attr "prefix" "evex") + (and (eq_attr "c86_attr" "other") +@@ -1662,7 +1684,7 @@ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_xy_load" 11 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_ssecvt_y_z" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecvt") + (and (eq_attr "mode" "OI,V8SF,V4DF") + (and (eq_attr "c86_attr" "other") +@@ -1672,7 +1694,7 @@ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_y_z" 8 + "c86-4g-m7-double,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_ssecvt_y_z_load" 15 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecvt") + (and (eq_attr "mode" "OI,V8SF,V4DF") + (and (eq_attr "c86_attr" "other") +@@ -1682,7 +1704,7 @@ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_y_z_load" 15 + "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_ssecvt_z" 4 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecvt") + (and (eq_attr "c86_attr" "other") + (and (eq_attr "mode" "XI,V16SF,V8DF") +@@ -1690,7 +1712,7 @@ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_z" 4 + "c86-4g-m7-double,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_ssecvt_z_load" 11 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecvt") + (and (eq_attr "c86_attr" "other") + (and (eq_attr "mode" "XI,V16SF,V8DF") +@@ -1698,7 +1720,7 @@ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_z_load" 11 + "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx_ssecvt" 4 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecvt") + (and (eq_attr "prefix" "!evex") + (and (eq_attr "mmx_isa" "base") +@@ -1706,7 +1728,7 @@ (define_insn_reservation "c86_4g_m7_avx_ssecvt" 4 + "c86-4g-m7-direct,c86-4g-m7-fpu2|c86-4g-m7-fpu3") + + (define_insn_reservation "c86_4g_m7_avx_ssecvt_load" 11 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecvt") + (and (eq_attr "prefix" "!evex") + (and (eq_attr "mmx_isa" "base") +@@ -1715,21 +1737,21 @@ (define_insn_reservation "c86_4g_m7_avx_ssecvt_load" 11 + + ;; CVTPI + (define_insn_reservation "c86_4g_m7_sse_ssecvt_pspi" 4 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecvt") + (and (eq_attr "mode" "SF,DI") + (eq_attr "memory" "none")))) + "c86-4g-m7-direct,c86-4g-m7-fpu1") + + (define_insn_reservation "c86_4g_m7_sse_ssecvt_pspi_load" 11 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecvt") + (and (eq_attr "mode" "SF,DI") + (eq_attr "memory" "load")))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1") + + (define_insn_reservation "c86_4g_m7_sse_ssecvt_pi" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecvt") + (and (not (eq_attr "mode" "SF,DI")) + (and (eq_attr "mmx_isa" "native") +@@ -1737,7 +1759,7 @@ (define_insn_reservation "c86_4g_m7_sse_ssecvt_pi" 5 + "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1") + + (define_insn_reservation "c86_4g_m7_sse_ssecvt_pi_load" 12 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssecvt") + (and (not (eq_attr "mode" "SF,DI")) + (and (eq_attr "mmx_isa" "native") +@@ -1759,8 +1781,22 @@ (define_insn_reservation "c86_4g_m7_avx512_muladd_load" 11 + (eq_attr "memory" "load")))) + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2") + ++(define_insn_reservation "c86_4g_m8_avx512_muladd" 5 ++ (and (eq_attr "cpu" "c86_4g_m8") ++ (and (eq_attr "type" "ssemuladd") ++ (and (eq_attr "c86_attr" "other") ++ (eq_attr "memory" "none")))) ++ "c86-4g-m7-direct,c86-4g-m7-fpu_0_2") ++ ++(define_insn_reservation "c86_4g_m8_avx512_muladd_load" 12 ++ (and (eq_attr "cpu" "c86_4g_m8") ++ (and (eq_attr "type" "ssemuladd") ++ (and (eq_attr "c86_attr" "other") ++ (eq_attr "memory" "load")))) ++ "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2") ++ + (define_insn_reservation "c86_4g_m7_avx512_muladd_madd" 4 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemuladd,sse") + (and (eq_attr "c86_attr" "madd,rcp") + (and (eq_attr "prefix" "evex") +@@ -1768,7 +1804,7 @@ (define_insn_reservation "c86_4g_m7_avx512_muladd_madd" 4 + "c86-4g-m7-direct,c86-4g-m7-fpu_0_2") + + (define_insn_reservation "c86_4g_m7_avx512_muladd_madd_load" 11 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "ssemuladd,sse") + (and (eq_attr "c86_attr" "madd,rcp") + (and (eq_attr "prefix" "evex") +@@ -1777,7 +1813,7 @@ (define_insn_reservation "c86_4g_m7_avx512_muladd_madd_load" 11 + + ;; SSE + (define_insn_reservation "c86_4g_m7_avx512_sse_range" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "c86_attr" "other") + (and (eq_attr "length_immediate" "!1") +@@ -1787,7 +1823,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_range" 1 + "c86-4g-m7-direct,c86-4g-m7-fpu_0_2") + + (define_insn_reservation "c86_4g_m7_avx512_sse_range_load" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "c86_attr" "other") + (and (eq_attr "length_immediate" "!1") +@@ -1797,7 +1833,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_range_load" 8 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2") + + (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_x" 2 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "c86_decode" "vector") + (and (eq_attr "mode" "TI") +@@ -1805,7 +1841,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_x" 2 + "c86-4g-m7-vector,c86-4g-m7-fpu_1_3x2") + + (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_x_load" 9 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "c86_decode" "vector") + (and (eq_attr "mode" "TI") +@@ -1813,7 +1849,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_x_load" 9 + "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3x2") + + (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_y" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "c86_decode" "vector") + (and (eq_attr "mode" "OI") +@@ -1821,7 +1857,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_y" 5 + "c86-4g-m7-vector,c86-4g-m7-fpu_1_3x3") + + (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_y_load" 12 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "c86_decode" "vector") + (and (eq_attr "mode" "OI") +@@ -1829,7 +1865,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_y_load" 12 + "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3x3") + + (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_z" 8 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "c86_decode" "vector") + (and (eq_attr "mode" "XI") +@@ -1837,7 +1873,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_z" 8 + "c86-4g-m7-vector,c86-4g-m7-fpu_1_3x6") + + (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_z_load" 15 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "c86_decode" "vector") + (and (eq_attr "mode" "XI") +@@ -1845,7 +1881,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_z_load" 15 + "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3x6") + + (define_insn_reservation "c86_4g_m7_avx512_sse_class" 4 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "c86_attr" "other") + (and (eq_attr "length_immediate" "1") +@@ -1854,7 +1890,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_class" 4 + "c86-4g-m7-double,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_sse_class_load" 11 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "c86_attr" "other") + (and (eq_attr "length_immediate" "1") +@@ -1863,7 +1899,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_class_load" 11 + "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_sse_class_z" 4 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "c86_attr" "other") + (and (eq_attr "length_immediate" "1") +@@ -1872,7 +1908,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_class_z" 4 + "c86-4g-m7-vector,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_sse_class_z_load" 11 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "c86_attr" "other") + (and (eq_attr "length_immediate" "1") +@@ -1881,7 +1917,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_class_z_load" 11 + "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx_sse" 5 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "c86_attr" "rcp,other") + (and (eq_attr "prefix" "!evex") +@@ -1889,7 +1925,7 @@ (define_insn_reservation "c86_4g_m7_avx_sse" 5 + "c86-4g-m7-direct,c86-4g-m7-fpu_0_1") + + (define_insn_reservation "c86_4g_m7_avx_sse_load" 12 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "c86_attr" "rcp,other") + (and (eq_attr "prefix" "!evex") +@@ -1898,7 +1934,7 @@ (define_insn_reservation "c86_4g_m7_avx_sse_load" 12 + + ;; SSE SQRT + (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_x" 14 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "mode" "SF,V4SF") + (and (eq_attr "c86_attr" "sqrt") +@@ -1906,7 +1942,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_x" 14 + "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x9") + + (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_xload" 21 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "mode" "SF,V4SF") + (and (eq_attr "c86_attr" "sqrt") +@@ -1914,7 +1950,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_xload" 21 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x9") + + (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_y" 14 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "mode" "V8SF") + (and (eq_attr "c86_attr" "sqrt") +@@ -1922,7 +1958,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_y" 14 + "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*9") + + (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_yload" 21 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "mode" "V8SF") + (and (eq_attr "c86_attr" "sqrt") +@@ -1930,7 +1966,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_yload" 21 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*9") + + (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_z" 26 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "mode" "V16SF") + (and (eq_attr "c86_attr" "sqrt") +@@ -1938,7 +1974,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_z" 26 + "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*22") + + (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_zload" 33 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "mode" "V16SF") + (and (eq_attr "c86_attr" "sqrt") +@@ -1946,7 +1982,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_zload" 33 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*22") + + (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_x" 20 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "mode" "DF,V2DF") + (and (eq_attr "c86_attr" "sqrt") +@@ -1954,7 +1990,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_x" 20 + "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x15") + + (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_xload" 27 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "mode" "DF,V2DF") + (and (eq_attr "c86_attr" "sqrt") +@@ -1962,7 +1998,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_xload" 27 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x15") + + (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_y" 20 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "mode" "V4DF") + (and (eq_attr "c86_attr" "sqrt") +@@ -1970,7 +2006,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_y" 20 + "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*15") + + (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_yload" 27 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "mode" "V4DF") + (and (eq_attr "c86_attr" "sqrt") +@@ -1978,7 +2014,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_yload" 27 + "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*15") + + (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_z" 38 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "mode" "V8DF") + (and (eq_attr "c86_attr" "sqrt") +@@ -1986,7 +2022,7 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_z" 38 + "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*34") + + (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_zload" 45 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "sse") + (and (eq_attr "mode" "V8DF") + (and (eq_attr "c86_attr" "sqrt") +@@ -1995,53 +2031,53 @@ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_zload" 45 + + ;; MSKLOG/MSKMOV + (define_insn_reservation "c86_4g_m7_avx512_msklog" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "msklog") + (eq_attr "c86_decode" "direct"))) + "c86-4g-m7-direct,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_msklog_vector" 4 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "msklog") + (eq_attr "c86_decode" "vector"))) + "c86-4g-m7-vector,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_mskmov_reg_k" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "mskmov") + (and (match_operand 0 "register_operand" "r") + (eq_attr "memory" "none")))) + "c86-4g-m7-double,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_mskmov_xy_k" 2 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "mskmov") + (ior (match_operand:V2DI 0 "register_operand" "v") + (match_operand:V4DI 0 "register_operand" "v")))) + "c86-4g-m7-double,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_mskmov_z_k" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "mskmov") + (match_operand:V8DI 0 "register_operand" "v"))) + "c86-4g-m7-vector,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_mskmov_k_k" 1 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "mskmov") + (and (match_operand 0 "register_operand" "k") + (match_operand 1 "register_operand" "k")))) + "c86-4g-m7-direct,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_mskmov_k_reg" 3 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "mskmov") + (and (match_operand 0 "register_operand" "k") + (match_operand 1 "register_operand" "r")))) + "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_1_3") + + (define_insn_reservation "c86_4g_m7_avx512_mskmov_k_m" 9 +- (and (eq_attr "cpu" "c86_4g_m7") ++ (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8") + (and (eq_attr "type" "mskmov") + (and (match_operand 0 "register_operand" "k") + (match_operand 1 "memory_operand")))) +diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc +index d17ad2515ea..6fbdabdbfac 100644 +--- a/gcc/config/i386/driver-i386.cc ++++ b/gcc/config/i386/driver-i386.cc +@@ -503,8 +503,10 @@ const char *host_detect_local_cpu (int argc, const char **argv) + processor = PROCESSOR_C86_4G_M4; + else if (model == 6) + processor = PROCESSOR_C86_4G_M6; +- else if (model >= 7) ++ else if (model == 7) + processor = PROCESSOR_C86_4G_M7; ++ else if (model >= 8) ++ processor = PROCESSOR_C86_4G_M8; + } + else if (vendor == VENDOR_CENTAUR) + { +@@ -821,6 +823,9 @@ const char *host_detect_local_cpu (int argc, const char **argv) + case PROCESSOR_C86_4G_M7: + cpu = "c86-4g-m7"; + break; ++ case PROCESSOR_C86_4G_M8: ++ cpu = "c86-4g-m8"; ++ break; + + default: + /* Use something reasonable. */ +diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc +index 1505963032f..6959b849431 100644 +--- a/gcc/config/i386/i386-c.cc ++++ b/gcc/config/i386/i386-c.cc +@@ -274,6 +274,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, + def_or_undef (parse_in, "__c86_4g_m7"); + def_or_undef (parse_in, "__c86_4g_m7__"); + break; ++ case PROCESSOR_C86_4G_M8: ++ def_or_undef (parse_in, "__c86_4g_m8"); ++ def_or_undef (parse_in, "__c86_4g_m8__"); ++ break; + /* use PROCESSOR_max to not set/unset the arch macro. */ + case PROCESSOR_max: + break; +@@ -461,6 +465,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, + case PROCESSOR_C86_4G_M7: + def_or_undef (parse_in, "__tune_c86_4g_m7__"); + break; ++ case PROCESSOR_C86_4G_M8: ++ def_or_undef (parse_in, "__tune_c86_4g_m8__"); ++ break; + case PROCESSOR_INTEL: + case PROCESSOR_GENERIC: + break; +diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc +index 98cf03eaa15..8622c0eab0b 100644 +--- a/gcc/config/i386/i386-options.cc ++++ b/gcc/config/i386/i386-options.cc +@@ -173,7 +173,9 @@ along with GCC; see the file COPYING3. If not see + #define m_C86_4G_M4 (HOST_WIDE_INT_1U<= 2.31, elfutils-devel >= 0.147, elfutils-libelf-devel >= 0.147, sharutils, gcc, gcc-c++, make BuildRequires: glibc-static, glibc-devel >= 2.4.90-13, gdb @@ -888,6 +891,9 @@ for cross toolchains %patch 3013 -p1 %patch 3014 -p1 %patch 3015 -p1 +%patch 3016 -p1 +%patch 3017 -p1 +%patch 3018 -p1 rm -f libphobos/testsuite/libphobos.gc/forkgc2.d @@ -2443,6 +2449,11 @@ end %changelog +* Wed Jul 01 2026 Kewen Lin - 12.3.1.8-5 +- [Type] sync +- [DESC] [X86] Support HYGON C86-4G-M8 processor +- Backport HYGON C86-4G-M8 support from fsf gcc upstream + * Fri Jun 12 2026 Kewen Lin - 12.3.1.8-4 - [Type] sync - [DESC] [X86] Support HYGON C86-4G series processors