From 2f93aed508a925cae61963ff01f802051d555b55 Mon Sep 17 00:00:00 2001 From: xinlongchen Date: Tue, 30 Jun 2026 18:55:51 +0800 Subject: [PATCH] performance tuning for x86 --- 0001-Enable-small-loop-unrolling-for-O2.patch | 505 ++++++++++++++++++ ...dd-br_mispredict_scale-in-cost-table.patch | 372 +++++++++++++ ...neric-tune-branch-misprediction-cost.patch | 36 ++ gcc.spec | 13 +- 4 files changed, 925 insertions(+), 1 deletion(-) create mode 100644 0001-Enable-small-loop-unrolling-for-O2.patch create mode 100644 0002-i386-Add-br_mispredict_scale-in-cost-table.patch create mode 100644 0003-x86-Increase-generic-tune-branch-misprediction-cost.patch diff --git a/0001-Enable-small-loop-unrolling-for-O2.patch b/0001-Enable-small-loop-unrolling-for-O2.patch new file mode 100644 index 0000000..8ee397e --- /dev/null +++ b/0001-Enable-small-loop-unrolling-for-O2.patch @@ -0,0 +1,505 @@ +From 3fbac0d575cfca08ff68c4184e08b589cdd0b67f Mon Sep 17 00:00:00 2001 +From: Hongyu Wang +Date: Tue, 30 Jun 2026 16:52:30 +0800 +Subject: [PATCH] Enable small loop unrolling for O2 + +Modern processors has multiple way instruction decoders +For x86, icelake/zen3 has 5 uops, so for small loop with <= 4 +instructions (usually has 3 uops with a cmp/jmp pair that can be +macro-fused), the decoder would have 2 uops bubble for each iteration +and the pipeline could not be fully utilized. + +Therefore, this patch enables loop unrolling for small size loop at O2 +to fullfill the decoder as much as possible. It turns on rtl loop +unrolling when targetm.loop_unroll_adjust exists and O2 plus speed only. +In x86 backend the default behavior is to unroll small loops with less +than 4 insns by 1 time. + +This improves 548.exchange2 by 9% on icelake and 7.4% on zen3 with +0.9% codesize increment. For other benchmarks the variants are minor +and overall codesize increased by 0.2%. + +The kernel image size increased by 0.06%, and no impact on eembc. + +gcc/ChangeLog: + + * common/config/i386/i386-common.cc (ix86_optimization_table): + Enable small loop unroll at O2 by default. + * config/i386/i386.cc (ix86_loop_unroll_adjust): Adjust unroll + factor if -munroll-only-small-loops enabled and -funroll-loops/ + -funroll-all-loops are disabled. + * config/i386/i386.h (struct processor_costs): Add 2 field + small_unroll_ninsns and small_unroll_factor. + * config/i386/i386.opt: Add -munroll-only-small-loops. + * loop-init.cc (pass_rtl_unroll_loops::gate): Enable rtl + loop unrolling for -O2-speed and above if target hook + loop_unroll_adjust exists. + (pass_rtl_unroll_loops::execute): Set UAP_UNROLL flag + when target hook loop_unroll_adjust exists. + * config/i386/x86-tune-costs.h: Update all processor costs + with small_unroll_ninsns = 4 and small_unroll_factor = 2. + +gcc/testsuite/ChangeLog: + + * gcc.dg/guality/loop-1.c: Add additional option + -mno-unroll-only-small-loops. + * gcc.target/i386/pr86270.c: Add -mno-unroll-only-small-loops. + * gcc.target/i386/pr93002.c: Likewise. + +Co-authored-by: Cursor +--- + gcc/common/config/i386/i386-common.cc | 1 + + gcc/config/i386/i386.cc | 18 +++++++ + gcc/config/i386/i386.h | 5 ++ + gcc/config/i386/i386.opt | 4 ++ + gcc/config/i386/x86-tune-costs.h | 68 +++++++++++++++++++++++++ + gcc/loop-init.cc | 10 ++-- + gcc/testsuite/gcc.dg/guality/loop-1.c | 2 + + gcc/testsuite/gcc.target/i386/pr86270.c | 2 +- + gcc/testsuite/gcc.target/i386/pr93002.c | 2 +- + 9 files changed, 107 insertions(+), 5 deletions(-) + +diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc +index e2877e0d547..8166f3fd673 100644 +--- a/gcc/common/config/i386/i386-common.cc ++++ b/gcc/common/config/i386/i386-common.cc +@@ -1687,6 +1687,7 @@ static const struct default_options ix86_option_optimization_table[] = + /* The STC algorithm produces the smallest code at -Os, for x86. */ + { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_algorithm_, NULL, + REORDER_BLOCKS_ALGORITHM_STC }, ++ { OPT_LEVELS_2_PLUS_SPEED_ONLY, OPT_munroll_only_small_loops, NULL, 1 }, + /* Turn off -fschedule-insns by default. It tends to make the + problem with not enough registers even worse. */ + { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 }, +diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc +index 37d3b141bd3..313b66037b1 100644 +--- a/gcc/config/i386/i386.cc ++++ b/gcc/config/i386/i386.cc +@@ -23575,6 +23575,24 @@ ix86_loop_unroll_adjust (unsigned nunroll, class loop *loop) + unsigned i; + unsigned mem_count = 0; + ++ /* Unroll small size loop when unroll factor is not explicitly ++ specified. */ ++ if (!(flag_unroll_loops ++ || flag_unroll_all_loops ++ || loop->unroll)) ++ { ++ nunroll = 1; ++ ++ /* Any explicit -f{no-}unroll-{all-}loops turns off ++ -munroll-only-small-loops. */ ++ if (ix86_unroll_only_small_loops ++ && !OPTION_SET_P (flag_unroll_loops) ++ && loop->ninsns <= ix86_cost->small_unroll_ninsns) ++ nunroll = ix86_cost->small_unroll_factor; ++ ++ return nunroll; ++ } ++ + if (!TARGET_ADJUST_UNROLL) + return nunroll; + +diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h +index 92763d03549..6faf80ac985 100644 +--- a/gcc/config/i386/i386.h ++++ b/gcc/config/i386/i386.h +@@ -219,6 +219,11 @@ struct processor_costs { + const char *const align_jump; /* Jump alignment. */ + const char *const align_label; /* Label alignment. */ + const char *const align_func; /* Function alignment. */ ++ ++ const unsigned small_unroll_ninsns; /* Insn count limit for small loop ++ to be unrolled. */ ++ const unsigned small_unroll_factor; /* Unroll factor for small loop to ++ be unrolled. */ + }; + + extern const struct processor_costs *ix86_cost; +diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt +index ed31cab0a46..5cc5cfb4602 100644 +--- a/gcc/config/i386/i386.opt ++++ b/gcc/config/i386/i386.opt +@@ -1226,3 +1226,7 @@ Enable vectorization for gather instruction. + mscatter + Target Alias(mtune-ctrl=, use_scatter, ^use_scatter) + Enable vectorization for scatter instruction. ++ ++munroll-only-small-loops ++Target Var(ix86_unroll_only_small_loops) Init(0) Save ++Enable conservative small loop unrolling. +diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h +index d2cc3ff2f47..c3c4683203c 100644 +--- a/gcc/config/i386/x86-tune-costs.h ++++ b/gcc/config/i386/x86-tune-costs.h +@@ -135,6 +135,8 @@ struct processor_costs ix86_size_cost = {/* costs for tuning for size */ + NULL, /* Jump alignment. */ + NULL, /* Label alignment. */ + NULL, /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + /* Processor costs (relative to an add) */ +@@ -244,6 +246,8 @@ struct processor_costs i386_cost = { /* 386 specific costs */ + "4", /* Jump alignment. */ + NULL, /* Label alignment. */ + "4", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + static stringop_algs i486_memcpy[2] = { +@@ -354,6 +358,8 @@ struct processor_costs i486_cost = { /* 486 specific costs */ + "16", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + static stringop_algs pentium_memcpy[2] = { +@@ -462,6 +468,8 @@ struct processor_costs pentium_cost = { + "16:8:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + static const +@@ -563,6 +571,8 @@ struct processor_costs lakemont_cost = { + "16:8:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes +@@ -679,6 +689,8 @@ struct processor_costs pentiumpro_cost = { + "16:11:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + static stringop_algs geode_memcpy[2] = { +@@ -786,6 +798,8 @@ struct processor_costs geode_cost = { + NULL, /* Jump alignment. */ + NULL, /* Label alignment. */ + NULL, /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + static stringop_algs k6_memcpy[2] = { +@@ -896,6 +910,8 @@ struct processor_costs k6_cost = { + "32:8:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "32", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + /* For some reason, Athlon deals better with REP prefix (relative to loops) +@@ -1007,6 +1023,8 @@ struct processor_costs athlon_cost = { + "16:8:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + /* K8 has optimized REP instruction for medium sized blocks, but for very +@@ -1127,6 +1145,8 @@ struct processor_costs k8_cost = { + "16:8:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for +@@ -1255,6 +1275,8 @@ struct processor_costs amdfam10_cost = { + "32:8:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "32", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + /* BDVER has optimized REP instruction for medium sized blocks, but for +@@ -1376,6 +1398,8 @@ const struct processor_costs bdver_cost = { + "16:8:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "11", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + +@@ -1529,6 +1553,8 @@ struct processor_costs znver1_cost = { + "16", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + /* ZNVER2 has optimized REP instruction for medium sized blocks, but for +@@ -1686,6 +1712,8 @@ struct processor_costs znver2_cost = { + "16", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + struct processor_costs znver3_cost = { +@@ -1818,6 +1846,8 @@ struct processor_costs znver3_cost = { + "16", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + /* This table currently replicates znver3_cost table. */ +@@ -1952,6 +1982,8 @@ struct processor_costs znver4_cost = { + "16", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + /* skylake_cost should produce code tuned for Skylake familly of CPUs. */ +@@ -2076,6 +2108,8 @@ struct processor_costs skylake_cost = { + "16:11:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + /* icelake_cost should produce code tuned for Icelake family of CPUs. +@@ -2202,6 +2236,8 @@ struct processor_costs icelake_cost = { + "16:11:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + /* alderlake_cost should produce code tuned for alderlake family of CPUs. */ +@@ -2322,6 +2358,8 @@ struct processor_costs alderlake_cost = { + "16:11:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + /* BTVER1 has optimized REP instruction for medium sized blocks, but for +@@ -2435,6 +2473,8 @@ const struct processor_costs btver1_cost = { + "16:8:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "11", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + static stringop_algs btver2_memcpy[2] = { +@@ -2545,6 +2585,8 @@ const struct processor_costs btver2_cost = { + "16:8:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "11", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + static stringop_algs pentium4_memcpy[2] = { +@@ -2654,6 +2696,8 @@ struct processor_costs pentium4_cost = { + NULL, /* Jump alignment. */ + NULL, /* Label alignment. */ + NULL, /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + static stringop_algs nocona_memcpy[2] = { +@@ -2766,6 +2810,8 @@ struct processor_costs nocona_cost = { + NULL, /* Jump alignment. */ + NULL, /* Label alignment. */ + NULL, /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + static stringop_algs atom_memcpy[2] = { +@@ -2876,6 +2922,8 @@ struct processor_costs atom_cost = { + "16:8:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + static stringop_algs slm_memcpy[2] = { +@@ -2986,6 +3034,8 @@ struct processor_costs slm_cost = { + "16:8:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + static stringop_algs tremont_memcpy[2] = { +@@ -3110,6 +3160,8 @@ struct processor_costs tremont_cost = { + "16:11:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + static stringop_algs intel_memcpy[2] = { +@@ -3220,6 +3272,8 @@ struct processor_costs intel_cost = { + "16:8:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + /* lujiazui_cost should produce code tuned for ZHAOXIN lujiazui CPU. */ +@@ -3335,6 +3389,8 @@ struct processor_costs lujiazui_cost = { + "16:11:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + /* yongfeng_cost should produce code tuned for ZHAOXIN yongfeng CPU. */ +@@ -3448,6 +3504,8 @@ struct processor_costs yongfeng_cost = { + "16:11:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + /* shijidadao_cost should produce code tuned for ZHAOXIN shijidadao CPU. */ +@@ -3561,6 +3619,8 @@ struct processor_costs shijidadao_cost = { + "16:11:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + /* Generic should produce code tuned for Core-i7 (and newer chips) +@@ -3680,6 +3740,8 @@ struct processor_costs generic_cost = { + "16:11:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + /* core_cost should produce code tuned for Core familly of CPUs. */ +@@ -3806,6 +3868,8 @@ struct processor_costs core_cost = { + "16:11:8", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + /* C86_4G_M4 has optimized REP instruction for medium sized blocks, but for +@@ -3958,6 +4022,8 @@ struct processor_costs c86_4g_m4_cost = { + "16", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; + + struct processor_costs c86_4g_m6_cost = c86_4g_m4_cost; +@@ -4083,4 +4149,6 @@ struct processor_costs c86_4g_m7_cost = { + "16", /* Jump alignment. */ + "0:0:8", /* Label alignment. */ + "16", /* Func alignment. */ ++ 4, /* Small unroll limit. */ ++ 2, /* Small unroll factor. */ + }; +diff --git a/gcc/loop-init.cc b/gcc/loop-init.cc +index 1e4f6cfd7fb..f1c71704116 100644 +--- a/gcc/loop-init.cc ++++ b/gcc/loop-init.cc +@@ -565,9 +565,12 @@ public: + {} + + /* opt_pass methods: */ +- virtual bool gate (function *) ++ virtual bool gate (function *fun) + { +- return (flag_unroll_loops || flag_unroll_all_loops || cfun->has_unroll); ++ return (flag_unroll_loops || flag_unroll_all_loops || cfun->has_unroll ++ || (targetm.loop_unroll_adjust ++ && optimize >= 2 ++ && optimize_function_for_speed_p (fun))); + } + + virtual unsigned int execute (function *); +@@ -583,7 +586,8 @@ pass_rtl_unroll_loops::execute (function *fun) + if (dump_file) + df_dump (dump_file); + +- if (flag_unroll_loops) ++ if (flag_unroll_loops ++ || targetm.loop_unroll_adjust) + flags |= UAP_UNROLL; + if (flag_unroll_all_loops) + flags |= UAP_UNROLL_ALL; +diff --git a/gcc/testsuite/gcc.dg/guality/loop-1.c b/gcc/testsuite/gcc.dg/guality/loop-1.c +index 1b1f6d32271..a32ea445a3f 100644 +--- a/gcc/testsuite/gcc.dg/guality/loop-1.c ++++ b/gcc/testsuite/gcc.dg/guality/loop-1.c +@@ -1,5 +1,7 @@ + /* { dg-do run } */ + /* { dg-options "-fno-tree-scev-cprop -fno-tree-vectorize -g" } */ ++/* { dg-additional-options "-mno-unroll-only-small-loops" { target ia32 } } */ ++ + + #include "../nop.h" + +diff --git a/gcc/testsuite/gcc.target/i386/pr86270.c b/gcc/testsuite/gcc.target/i386/pr86270.c +index 81841ef5bd7..cbc9fbb0450 100644 +--- a/gcc/testsuite/gcc.target/i386/pr86270.c ++++ b/gcc/testsuite/gcc.target/i386/pr86270.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O2" } */ ++/* { dg-options "-O2 -mno-unroll-only-small-loops" } */ + + int *a; + long len; +diff --git a/gcc/testsuite/gcc.target/i386/pr93002.c b/gcc/testsuite/gcc.target/i386/pr93002.c +index 0248fcc00a5..f75a847f75d 100644 +--- a/gcc/testsuite/gcc.target/i386/pr93002.c ++++ b/gcc/testsuite/gcc.target/i386/pr93002.c +@@ -1,6 +1,6 @@ + /* PR target/93002 */ + /* { dg-do compile } */ +-/* { dg-options "-O2" } */ ++/* { dg-options "-O2 -mno-unroll-only-small-loops" } */ + /* { dg-final { scan-assembler-not "cmp\[^\n\r]*-1" } } */ + + volatile int sink; +-- +2.43.7 + diff --git a/0002-i386-Add-br_mispredict_scale-in-cost-table.patch b/0002-i386-Add-br_mispredict_scale-in-cost-table.patch new file mode 100644 index 0000000..a3d421b --- /dev/null +++ b/0002-i386-Add-br_mispredict_scale-in-cost-table.patch @@ -0,0 +1,372 @@ +From 75eb009461e35b867013e50e61fd35c13469b078 Mon Sep 17 00:00:00 2001 +From: Hongyu Wang +Date: Tue, 30 Jun 2026 16:53:59 +0800 +Subject: [PATCH] i386: Add br_mispredict_scale in cost table. + +For later processors, the pipeline went deeper so the penalty for +untaken branch can be larger than before. Add a new parameter +br_mispredict_scale to describe the penalty, and adopt to +noce_max_ifcvt_seq_cost hook to allow longer sequence to be +converted with cmove. + +This improves cpu2017 544 with -Ofast -march=native for 14% on P-core +SPR, and 8% on E-core SRF. No other regression observed. + +gcc/ChangeLog: + + * config/i386/i386.cc (ix86_noce_max_ifcvt_seq_cost): Adjust + cost with ix86_tune_cost->br_mispredict_scale. + * config/i386/i386.h (processor_costs): Add br_mispredict_scale. + * config/i386/x86-tune-costs.h: Add new br_mispredict_scale to + all processor_costs, in which icelake_cost/alderlake_cost + with value COSTS_N_INSNS (2) + 3 and other processor with value + COSTS_N_INSNS (2). + +gcc/testsuite/ChangeLog: + + * gcc.target/i386/cmov12.c: New test. + +Co-authored-by: Cursor +--- + gcc/config/i386/i386.cc | 8 +++++- + gcc/config/i386/i386.h | 2 ++ + gcc/config/i386/x86-tune-costs.h | 34 ++++++++++++++++++++++++++ + gcc/testsuite/gcc.target/i386/cmov12.c | 20 +++++++++++++++ + 4 files changed, 63 insertions(+), 1 deletion(-) + create mode 100644 gcc/testsuite/gcc.target/i386/cmov12.c + +diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc +index 313b66037b1..997d6ef2ba2 100644 +--- a/gcc/config/i386/i386.cc ++++ b/gcc/config/i386/i386.cc +@@ -23043,7 +23043,13 @@ ix86_max_noce_ifcvt_seq_cost (edge e) + return param_max_rtl_if_conversion_unpredictable_cost; + } + +- return BRANCH_COST (true, predictable_p) * COSTS_N_INSNS (2); ++ /* For modern machines with deeper pipeline, the penalty for branch ++ misprediction could be higher than before to reset the pipeline ++ slots. Add parameter br_mispredict_scale as a factor to describe ++ the impact of reseting the pipeline. */ ++ ++ return BRANCH_COST (true, predictable_p) ++ * ix86_tune_cost->br_mispredict_scale; + } + + /* Return true if SEQ is a good candidate as a replacement for the +diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h +index 6faf80ac985..77900bf4b13 100644 +--- a/gcc/config/i386/i386.h ++++ b/gcc/config/i386/i386.h +@@ -224,6 +224,8 @@ struct processor_costs { + to be unrolled. */ + const unsigned small_unroll_factor; /* Unroll factor for small loop to + be unrolled. */ ++ const int br_mispredict_scale; /* Branch mispredict scale for ifcvt ++ threshold. */ + }; + + extern const struct processor_costs *ix86_cost; +diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h +index c3c4683203c..adc860d0f74 100644 +--- a/gcc/config/i386/x86-tune-costs.h ++++ b/gcc/config/i386/x86-tune-costs.h +@@ -137,6 +137,7 @@ struct processor_costs ix86_size_cost = {/* costs for tuning for size */ + NULL, /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + /* Processor costs (relative to an add) */ +@@ -248,6 +249,7 @@ struct processor_costs i386_cost = { /* 386 specific costs */ + "4", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + static stringop_algs i486_memcpy[2] = { +@@ -360,6 +362,7 @@ struct processor_costs i486_cost = { /* 486 specific costs */ + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + static stringop_algs pentium_memcpy[2] = { +@@ -470,6 +473,7 @@ struct processor_costs pentium_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + static const +@@ -573,6 +577,7 @@ struct processor_costs lakemont_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes +@@ -691,6 +696,7 @@ struct processor_costs pentiumpro_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + static stringop_algs geode_memcpy[2] = { +@@ -800,6 +806,7 @@ struct processor_costs geode_cost = { + NULL, /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + static stringop_algs k6_memcpy[2] = { +@@ -912,6 +919,7 @@ struct processor_costs k6_cost = { + "32", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + /* For some reason, Athlon deals better with REP prefix (relative to loops) +@@ -1025,6 +1033,7 @@ struct processor_costs athlon_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + /* K8 has optimized REP instruction for medium sized blocks, but for very +@@ -1147,6 +1156,7 @@ struct processor_costs k8_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for +@@ -1277,6 +1287,7 @@ struct processor_costs amdfam10_cost = { + "32", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + /* BDVER has optimized REP instruction for medium sized blocks, but for +@@ -1400,6 +1411,7 @@ const struct processor_costs bdver_cost = { + "11", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + +@@ -1555,6 +1567,7 @@ struct processor_costs znver1_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + /* ZNVER2 has optimized REP instruction for medium sized blocks, but for +@@ -1714,6 +1727,7 @@ struct processor_costs znver2_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + struct processor_costs znver3_cost = { +@@ -1848,6 +1862,7 @@ struct processor_costs znver3_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + /* This table currently replicates znver3_cost table. */ +@@ -1984,6 +1999,7 @@ struct processor_costs znver4_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + /* skylake_cost should produce code tuned for Skylake familly of CPUs. */ +@@ -2110,6 +2126,7 @@ struct processor_costs skylake_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + /* icelake_cost should produce code tuned for Icelake family of CPUs. +@@ -2238,6 +2255,7 @@ struct processor_costs icelake_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2) + 3, /* Branch mispredict scale. */ + }; + + /* alderlake_cost should produce code tuned for alderlake family of CPUs. */ +@@ -2360,6 +2378,7 @@ struct processor_costs alderlake_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2) + 3, /* Branch mispredict scale. */ + }; + + /* BTVER1 has optimized REP instruction for medium sized blocks, but for +@@ -2475,6 +2494,7 @@ const struct processor_costs btver1_cost = { + "11", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + static stringop_algs btver2_memcpy[2] = { +@@ -2587,6 +2607,7 @@ const struct processor_costs btver2_cost = { + "11", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + static stringop_algs pentium4_memcpy[2] = { +@@ -2698,6 +2719,7 @@ struct processor_costs pentium4_cost = { + NULL, /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + static stringop_algs nocona_memcpy[2] = { +@@ -2812,6 +2834,7 @@ struct processor_costs nocona_cost = { + NULL, /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + static stringop_algs atom_memcpy[2] = { +@@ -2924,6 +2947,7 @@ struct processor_costs atom_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + static stringop_algs slm_memcpy[2] = { +@@ -3036,6 +3060,7 @@ struct processor_costs slm_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + static stringop_algs tremont_memcpy[2] = { +@@ -3162,6 +3187,7 @@ struct processor_costs tremont_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + static stringop_algs intel_memcpy[2] = { +@@ -3274,6 +3300,7 @@ struct processor_costs intel_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + /* lujiazui_cost should produce code tuned for ZHAOXIN lujiazui CPU. */ +@@ -3391,6 +3418,7 @@ struct processor_costs lujiazui_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + /* yongfeng_cost should produce code tuned for ZHAOXIN yongfeng CPU. */ +@@ -3506,6 +3534,7 @@ struct processor_costs yongfeng_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + /* shijidadao_cost should produce code tuned for ZHAOXIN shijidadao CPU. */ +@@ -3621,6 +3650,7 @@ struct processor_costs shijidadao_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + /* Generic should produce code tuned for Core-i7 (and newer chips) +@@ -3742,6 +3772,7 @@ struct processor_costs generic_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + /* core_cost should produce code tuned for Core familly of CPUs. */ +@@ -3870,6 +3901,7 @@ struct processor_costs core_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + /* C86_4G_M4 has optimized REP instruction for medium sized blocks, but for +@@ -4024,6 +4056,7 @@ struct processor_costs c86_4g_m4_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; + + struct processor_costs c86_4g_m6_cost = c86_4g_m4_cost; +@@ -4151,4 +4184,5 @@ struct processor_costs c86_4g_m7_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ ++ COSTS_N_INSNS (2), /* Branch mispredict scale. */ + }; +diff --git a/gcc/testsuite/gcc.target/i386/cmov12.c b/gcc/testsuite/gcc.target/i386/cmov12.c +new file mode 100644 +index 00000000000..3be43d477b6 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/i386/cmov12.c +@@ -0,0 +1,20 @@ ++/* { dg-do compile { target { ! ia32 } } } */ ++/* { dg-options "-O2 -mavx2 -mtune=sapphirerapids" } */ ++/* { dg-final { scan-assembler-times "cmovg" 3 } } */ ++ ++void foo(int *a, int n, int k) ++{ ++ int j, v; ++ ++ v = a[k - 1]; ++ while (k <= n / 2) { ++ j = k + k; ++ if ((j < n) && (a[j - 1] < a[j])) ++ j++; ++ if (v >= a[j - 1]) ++ break; ++ a[k - 1] = a[j - 1]; ++ k = j; ++ } ++ a[k - 1] = v; ++} +-- +2.43.7 + diff --git a/0003-x86-Increase-generic-tune-branch-misprediction-cost.patch b/0003-x86-Increase-generic-tune-branch-misprediction-cost.patch new file mode 100644 index 0000000..f7cf275 --- /dev/null +++ b/0003-x86-Increase-generic-tune-branch-misprediction-cost.patch @@ -0,0 +1,36 @@ +From 52cd02606b906160bf47001a00b446c35d46f15f Mon Sep 17 00:00:00 2001 +From: Lili Cui +Date: Wed, 24 Jun 2026 00:05:31 -0700 +Subject: [PATCH] x86: Increase generic tune branch misprediction cost + +Increase the branch misprediction scale for generic tuning from +COSTS_N_INSNS (2) to COSTS_N_INSNS (2) + 3. + +Modern CPUs have deeper pipelines, making branch mispredictions more +expensive. Increasing this cost encourages if-conversion, avoiding +pipeline stalls from mispredicted branches. + +This improves 544.nab_r (-O2) by 12.7% on GNR and 12.1% on Znver5 with +single-copy. + +gcc/ChangeLog: + + * config/i386/x86-tune-costs.h (generic_cost): Increase branch + mispredict scale from COSTS_N_INSNS (2) to COSTS_N_INSNS (2) + 3. +--- + gcc/config/i386/x86-tune-costs.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h +index cc9de64394e07..bc3bb69434919 100644 +--- a/gcc/config/i386/x86-tune-costs.h ++++ b/gcc/config/i386/x86-tune-costs.h +@@ -3772,7 +3772,7 @@ struct processor_costs generic_cost = { + "16", /* Func alignment. */ + 4, /* Small unroll limit. */ + 2, /* Small unroll factor. */ +- COSTS_N_INSNS (2), /* Branch mispredict scale. */ ++ COSTS_N_INSNS (2) + 3, /* Branch mispredict scale. */ + }; + + /* core_cost should produce code tuned for Core familly of CPUs. */ diff --git a/gcc.spec b/gcc.spec index 6c29dfc..d015a6e 100644 --- a/gcc.spec +++ b/gcc.spec @@ -1,6 +1,6 @@ %global gcc_version 12.3.1.8 %global gcc_major 12 -%global gcc_release 4 +%global gcc_release 5 %global isl_version 0.18 %global tgcc_summary Tencent Compiler %global _unpackaged_files_terminate_build 0 @@ -155,6 +155,10 @@ Patch3012: 0001-Disparage-slightly-for-the-alternative-which-move-DF.patch Patch3013: HYGON-0001-i386-Support-HYGON-c86-4g-series-processors.patch Patch3014: HYGON-0002-i386-Adjust-some-c86-4g-.md-modeling-to-reduce-build.patch Patch3015: HYGON-0003-i386-Refine-c86-4g-fdiv-scheduling-model.patch +# x86 performance tuning: enable small loop unrolling at O2 and model branch mispredict cost. +Patch3016: 0001-Enable-small-loop-unrolling-for-O2.patch +Patch3017: 0002-i386-Add-br_mispredict_scale-in-cost-table.patch +Patch3018: 0003-x86-Increase-generic-tune-branch-misprediction-cost.patch BuildRequires: binutils >= 2.31, elfutils-devel >= 0.147, elfutils-libelf-devel >= 0.147, sharutils, gcc, gcc-c++, make BuildRequires: glibc-static, glibc-devel >= 2.4.90-13, gdb @@ -888,6 +892,9 @@ for cross toolchains %patch 3013 -p1 %patch 3014 -p1 %patch 3015 -p1 +%patch 3016 -p1 +%patch 3017 -p1 +%patch 3018 -p1 rm -f libphobos/testsuite/libphobos.gc/forkgc2.d @@ -2443,6 +2450,10 @@ end %changelog +* Tue Jun 30 2026 Xinlong Chen - 12.3.1.8-5 +- [Type] sync +- [DESC] performance tuning for x86: enable small loop unrolling at O2 and model branch mispredict cost. + * Fri Jun 12 2026 Kewen Lin - 12.3.1.8-4 - [Type] sync - [DESC] [X86] Support HYGON C86-4G series processors -- Gitee